6. (5pts) Using four 1-bit full adders only to design a four-bit
combinational Excess-3 to BCD converter. Show the block diagram and
label all inputs and outputs
1)
A. In a 1 bit half adder which design is the sizing of the
transistor most area efficient, CMOS logic, transmission gate, or
dynamic logic. Explain.
B. If the W/L of the transistors at gate level are the same,
which one will be the fastest driving the same amount of load.
Explain.
C. Which is the most power efficient?
(i) Design an 8-bit ripple adder which can add together two
8-bit numbers, inside a hierarchical block. Explain your design.
Name your block with your student number: eg “123456 ripple adder”.
(ii) Test your circuit in block form, showing four example
additions with manual calculations to show they are correct. [
Problem 3.73 (1-bit full adder using carry lookahead – gate
level circuit)
3.73 Design a 4-bit full adder using carry
look-ahead rather than ripple carry.