Question

Please Create the Verilog/Vivado Code For:

An LFSR Pseudonumber generator, and the testbench for test it,

please comment and explain the answer as much as possible,(Make your own code, even it is more simple, but do not copy from others sources on the internet)

if possible, post Pic of the waveform simulation!

Answer 1

Answer 1)

Verilog Code for the 4 bit LFSR is shown below

module lfsr (Data, Load, Clock, Out);
input [3:0] Data;
input Load;
input Clock;
output [3:0] Out;

reg [3:0] temp;

always @ (posedge Clock)
begin   
if (Load)
temp <= Data;
else
temp <= {!(temp[2]^temp[0]), temp[3], temp[2], temp[1]};
end

assign Out = temp;

endmodule

Testbench for the above LFSR is shown below:-

module lfsr_tb;
reg [3:0] Data;
reg Load, Clock;
wire [3:0] Out;

lfsr m1 (.Clock(Clock), .Load(Load), .Data(Data), .Out(Out));

initial
begin
Clock = 1'b0;
forever #5 Clock = ~Clock;
end

initial
begin
Data = 4'b1100;
Load = 1'b1;
@(negedge Clock);
Load = 1'b0;
repeat(20)
@(negedge Clock);
$finish;
end

endmodule

Waveform for the LFSR is :-