In: Electrical Engineering
Verilog code to make 8bit bcd to 8bit binary please
with testbench
Code :
Output
Test_bench:
Output :
Main_code :
`timescale 1ns / 1ps
module bcd_binary(in_bdc,out_binary);
input [7:0] in_bdc; //declaring input and output
output [7:0]out_binary;
wire [3:0]a,b;
assign a = in_bdc[3:0]; //assigning lsb four bits to a
assign b = in_bdc[7:4]; //msb four bits to b
assign out_binary = b*10+a; //converting that into binary
endmodule
Test_bench :
`timescale 1ns / 1ps
module test_bcd();
reg [7:0] in_bdc;
wire [7:0] out_binary;
reg [3:0]a,b;
bcd_binary x(in_bdc,out_binary); //instantiation our main code
initial
$monitor("input = %b | output = %b ",in_bdc,out_binary);
//displaying results
initial
begin
#20 in_bdc = 8'b00011000; //giving some random inputs
#20 in_bdc = 8'b00100110;
#20 in_bdc = 8'b00110001;
#50 $finish; //finishing
end
endmodule