Question

In: Computer Science

Computer Architecture Theme: External Memory Discuss the effectiveness of data striping in RAID 0 for the...

Computer Architecture

Theme: External Memory

Discuss the effectiveness of data striping in RAID 0 for the following two cases:

  • A single process requests large data sets
  • Multiple processes request several small sized data

Solutions

Expert Solution

The effectiveness of data stripping in raid 0 for a single process request large data set will be very why because of the fact that we will be requesting data from several disk which means data stripping will be very fast as the bandwidth as many disks will provide bandwidth of single drive into total number of disk which means that if we have three drives times the bandwidth of single drive as we are requesting last data set so our drivers will have to fetch the command single time or we have to instruct the drive a single time for fetching the data.

The effectiveness of data striping in raid 0 for multiple processes requesting small size data will be less because of the fact that the bandwidth of the drives has increased but they continuously have to return the fetch the data and get the details of the another set of data that they need to fetch this takes time and the effectiveness of data stripping in raid0 for multiple processes requesting small size data.


Related Solutions

Computer Architecture Theme: External Memory Very briefly discuss flash memory?
Computer Architecture Theme: External Memory Very briefly discuss flash memory?
Computer Architecture Theme: External Memory Very briefly define the seven RAID levels, providing information about stripe...
Computer Architecture Theme: External Memory Very briefly define the seven RAID levels, providing information about stripe size, synchronization, data transfer rate and their applications. (total less than a page)
Computer Architecture Theme: External Memory (DISK/CD) Define rotational delay, access time and transfer time. Does the...
Computer Architecture Theme: External Memory (DISK/CD) Define rotational delay, access time and transfer time. Does the hard drive/CDROM run on CLV or CAV? Why is the capacity of DVD more than a CD?
Course: Computer Architecture Theme: Internal Memory What is parity bitHow do the following work: flash memory,...
Course: Computer Architecture Theme: Internal Memory What is parity bitHow do the following work: flash memory, STT-RAM, PCRAM, ReRAM?? What is Hamming code? Give examples.
Course: Computer Architecture Theme: Internal Memory What are the differences among EPROM, EEPROM? What is a...
Course: Computer Architecture Theme: Internal Memory What are the differences among EPROM, EEPROM? What is a DDR SDRAM? How does an SDRAM differ from a DRAM? What is burst mode? What do you understand by interleaved memory?
Course: Computer Architecture Theme: Internal Memory Draw the diagram of a typical 16 Mb DRAM (4M...
Course: Computer Architecture Theme: Internal Memory Draw the diagram of a typical 16 Mb DRAM (4M X 4) and explain its action. Draw the diagram of an SRAM cell and explain its action.
About Cache, computer organization, computer architecture, computer science. Cache Question: A[0] is at memory address 0x0FED...
About Cache, computer organization, computer architecture, computer science. Cache Question: A[0] is at memory address 0x0FED CBA0. Array B[] is right after array A[] in the data memory. Both arrays have 10 integers Based on memory address for A[0] of 32 bits, i know that the cache index and tag is 27 bits, offset is 4 bits and index is 1 bit. Q: Will the tag and cache index change for A[8] and B[8]? And how will it change? I...
Course: Computer Architecture (Theme: Input-Output) A computer consists of a processor and an I/O device D...
Course: Computer Architecture (Theme: Input-Output) A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a max of 2 MIPS. An average instruction requires 5 machine cycles, 3 of which use the memory bus. A memory read/write operation uses 1 m/c cycle. Suppose that the processor is continuously executing “background” programs that require 96% of the instruction rate...
Discuss bootstrap processor and application processor in the context of shared memory architecture.
Discuss bootstrap processor and application processor in the context of shared memory architecture.
We are planning to use Raid Level-0. We have a data of size 2KB and we...
We are planning to use Raid Level-0. We have a data of size 2KB and we would like to create some blocks where each block will hold 4 Byte. We have total 5 disks named Disk0,Disk1,Disk2,Disk3,Disk4. The block number is starting from Block1. How many blocks will be stored by Disk1? ------------------------------------------------------------------------------------------------------------------------------- We are planning to use Raid Level-0. We have a data of size 2KB and we would like to create some blocks where each block will hold 4...
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT