Question

In: Computer Science

Discuss bootstrap processor and application processor in the context of shared memory architecture.

Discuss bootstrap processor and application processor in the context of shared memory architecture.

Solutions

Expert Solution

In a shared memory design, devices exchange data by writing to and reading from a pool of shared memory as shown within the figure. not like a shared bus design, during a shared memory design, there ar solely point-to-point connections between the device and also the shared memory, somewhat easing the board style and layout problems. Also, every interface will run at full information measure all the time, that the overall cloth information measure is way beyond in shared bus architectures.


In the shared-memory design, the complete memory, i.e., main memory and disks, is shared by all processors. A special, quick interconnection network (e.g., a high-speed bus or a cross-bar switch) permits any processor to access any a part of the memory in parallel. All processors ar below the management of one software that makes it simple to trot out load leveling. it's conjointly terribly economical since processors will communicate via the most memory.

Shared-memory is that the field model adopted by recent servers supported cruciform multiprocessors (SMP). it's been employed by many parallel information system prototypes and merchandise because it makes software package porting simple, mistreatment each inter-query and intra-query similarity. Shared-memory has 2 advantages: simplicity and cargo leveling. Since directory and management data (e.g., lock tables) ar shared by all processors.

Bootstrap processor:

When a automatic data processing system is 1st turned on (cold boot or reset), or once it's restarted while not turning the facility off (warm boot or reset), it should run a series of tests to see the identity and standing of its part elements, load essential package, e.g. the software, and establish communications among the part elements. This start-up method is observed as bootstrapping or booting to replicate the very fact that the system turns itself on incrementally. Typically, the individual processors every check their elements and interfaces. One methodor is then elect from their range to ascertain communications with the remainder of the system and complete the system-wide steps of the bootstrapping process. the chosen processor is that the bootstrap processor. In Intel processors and processors compatible with the Intel design, the bootstrapping method is initiated by declarative a reset signal that's input to every processor. the current invention isn't restricted to a selected reset signal or condition, and should be enforced with any of the reset indicators used by varied processor architectures.

The present invention could be a system and methodology for choosing a bootstrap processor (BSP) during a multi-processor system while not relation to memory, chipset logic, and different platform elements, and while not want for dedicated buses or logic devices. In one embodiment, part processors of the multi-processor system communicate among themselves and with a non-volatile memory location employing a system bus. The invention is enforced through inter-processor messages within the kind of inter-processor interrupts (IPIs), power management interrupts (PMIs), and comparable communication protocols.

Application processor:

An application processor could be a special reasonably microchip. the applying processor denomination came out of the cellular trade. during a mobile device, it refers to a chip used for the first process of mobile phone and different sensible functions. this can be in distinction with the chips that handle background functions like running the show, handling wireless communications and managing power drain.

One huge distinction between a microchip ANd an application processor is their physical packaging. several microprocessors ar commonplace ICs with a regular half range. In distinction, mobile application processors ar additional usually systems on a chip (SoC) that incorporate the information science of 1 or additional processor cores beside different adjuvant functions. Aplication processors usually run a mobile software surroundings, essentially a specialised RTOS, in addition as applications package.


Related Solutions

Computer Architecture Theme: External Memory Very briefly discuss flash memory?
Computer Architecture Theme: External Memory Very briefly discuss flash memory?
Explain the below concepts in depth. Server virtualization Application virtualization Processor and memory virtualization Network virtualization...
Explain the below concepts in depth. Server virtualization Application virtualization Processor and memory virtualization Network virtualization Data and storage virtualization
(terza/seconda) Question: Discuss the architecture of the application WA( the chat application with green icon and...
(terza/seconda) Question: Discuss the architecture of the application WA( the chat application with green icon and a phone) (incorrectly written) in terms of its protocols. Address and discuss all the essential protocols used by WA( the chat application with green icon and a phone) (incorrectly written) for communication. PLEASE write your answer in your own words!! cheers
discuss the relevance of Responsible Stewardship in the context of economic analysis and organizational architecture.
discuss the relevance of Responsible Stewardship in the context of economic analysis and organizational architecture.
Computer Architecture Theme: External Memory Discuss the effectiveness of data striping in RAID 0 for the...
Computer Architecture Theme: External Memory Discuss the effectiveness of data striping in RAID 0 for the following two cases: A single process requests large data sets Multiple processes request several small sized data
how to accept string from shared memory using c language ?
how to accept string from shared memory using c language ?
Course: Computer Architecture Theme: Internal Memory What is parity bitHow do the following work: flash memory,...
Course: Computer Architecture Theme: Internal Memory What is parity bitHow do the following work: flash memory, STT-RAM, PCRAM, ReRAM?? What is Hamming code? Give examples.
At the initial stage of each instruction cycle, the processor fetches an instruction from memory. The...
At the initial stage of each instruction cycle, the processor fetches an instruction from memory. The processor interprets the instruction and performs the required action. Provide illustration of the process with a thorough explanation on the rudimentary instruction cycles the processor follows to execute fundamental instructions. Discuss how this processor interacts with the cache memory to give output speedily.
Information architecture can be simply defined as organizing shared information. There are many different ways to...
Information architecture can be simply defined as organizing shared information. There are many different ways to organize web sites, including by audience, task, or topic. Discuss how a web site that you visit often is organized by audience, task, or topic. Provide a link to the site and support your argument with specific examples from the site.
The IBM System/370 architecture uses a two-level memory structure and refers to the
The IBM System/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described earlier in this chapter. For the basic 370 architecture, the page size may be either 2 Kbytes or 4 Kbytes, and the segment size is fixed at either 64 Kbytes or 1 Mbyte. For the 370/XA and 370/ESA architectures, the page size is 4 Kbytes and the segment size is 1...
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT