Question

In: Computer Science

Course: Computer Architecture (Theme: Input-Output) A computer consists of a processor and an I/O device D...

Course: Computer Architecture (Theme: Input-Output)

  1. A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a max of 2 MIPS. An average instruction requires 5 machine cycles, 3 of which use the memory bus. A memory read/write operation uses 1 m/c cycle. Suppose that the processor is continuously executing “background” programs that require 96% of the instruction rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is used to transfer very large amounts of data between M and D.
    1. If programmed I/O is used and each one word transfer requires the processor to execute 3 instructions, estimate the max I/O data transfer rate in words/sec possible through D?
    2. Estimate the same rate if DMA is used?

Solutions

Expert Solution

Solution:

A.

It is given that the processor requires 96% of the CPU time and during this time no I/O operations are performed.

Therefore, the processor can only devote 4% i.e. 4/100 (0.04) of its time to I/O.

Also, it is given that the processor can execute a max of 2 MIPS i.e. 2 x 106 instructions per second

Thus, the maximum I/O instruction execution rate is 2 x 106 x 0.04 = 80,000 instructions per second

Hence, the max I/O data transfer rate in words/sec possible through D is

                                                              = 80000/3

= 26,6666.67 words/sec


B.
It is given that an average instruction requires 5 machine cycles out of which 3 of them use the memory bus.

So only 2 cycles are left for DMA to use for 96% of the time.

                       i.e. for 96% of the time DMA uses 0.96 x 2 cycles

For rest 4% time, all cycles are available, so DMA uses

                       i.e. for 4% of the time DMA uses 0.04 x 5 cycles

Therefore, the number of machine cycles available for DMA is

(0.96 x 2 + 0.04 x 5) cycles

Also, it is given that the processor can execute a max of 2 MIPS i.e. 2 x 106 instructions per second. So, the rate of transfer is
=
2 x 106 x (0.96 x 2 + 0.04 x 5)
  = 4.24 x 106


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