Question

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Cache Question:

A[0] is at memory address 0x0FED CBA0. Array B[] is right after array A[] in the data memory.

Both arrays have 10 integers

Based on memory address for A[0] of 32 bits, i know that the cache index and tag is 27 bits, offset is 4 bits and index is 1 bit.

Q: Will the tag and cache index change for A[8] and B[8]? And how will it change?

I personally feel that tag and cache index will not change for A[8]. But i'm not too sure about B[8]

Q: Does the cache behaviour affect the A[8] and B[8]?

E.g. Direct mapped cache vs 2-way set-associative cache

Answer 1

Q: Will the tag and cache index change for A[8] and B[8]? And how will it change?

Since the offset is 4 bits, which means block size = 2⁴ = 16 bytes and since each integer requires 4 bytes of storage, hence there will be 4 elements per block and hence element A[8] and B[8] will not be in same block in main memory. Since their blocks are different, hence their tag field will definitely be different although they will have same index because there are only 2 cache blocks ( since index field is 1 bit, hence number of cache blocks = 2¹ = 2 blocks) and hence A[8] to B[1] will reside in one block, B[2] to B[5] in other block and then B[6] to B[8] in same block as A[8] to B[1].

Tag field of A[8] and B[8] will always be different as long as block size is 16 bytes.

Let calculate tag field for B[8]. Since there are 10 elements in array A and then 8 elements of array B are before B[8]. Hence B[8] is 19^thelement if we combine array A and B and so B[8] is 18 elements ahead of A[0].

Hence the address of B[8] = address of A[8] + 18*4 = address of A[8] + 72 = address of A[8] + 0x48

=  0x0FED CBA0 + 0x48 =   0x0FED CBE8 = 1111111011011100101111101000

Now the tag filed of B[8] will be obtained by taking first 27 bits of binary i.e. 1111111011011100101111 will be tag field for B[8]

Does the cache behaviour affect the A[8] and B[8]?

Yes, if we use direct mapped then since A[8] and B[8] have same cache index, hence they both can never be simultaneously present in cache but if we use 2-way set associative memory then since there are only 2 cache blocks which means only 1 set, hence it is possible that they could be simultaneously be present in cache.

Please comment for any clarification.