Question

What are the differences between the programming languages of VHDL and Verilog? Why use one over the other?

Answer 1

Verilog was the first hardware description language, it was proprietary and only used for simulation originally. It was designed to be like “C”: easy to code and run. At the lowest level of gates it is easier to read than a spice deck. To this day it is the preferred way netlists are transferred between tools.

VHDL was created as a cooperative standard HDL for design specification and simulation. It had to have strict type definitions, libraries and information hiding capabilities to be useful as a specification language. It is based on ADA, which is more like PASCAL than like the loosely typed “C” language of the time.

Synthesis tools first targeted VHDL since it was an open standard. Later Verilog was made open because people would not invest in a proprietary language. The synthesis tools then accepted Verilog as a HDL. Verilog has gone through iterations to add types like “signed” and “unsigned” and libraries.

I would say VHDL is a better language for system design and simulation because it is general. You could simulate a moon landing in VHDL because you can define arbitrary types and modify the event queue. But to use VHDL for synthesis you need to adhere to a small subset and particular types.

It takes longer to do a design in VHDL than in Verilog because VHDL does not have the simple semantics of “1=VDD” and “0=GND”. If you come from a schematic capture background or you need to do a lot of gate level design you would find Verilog easier to use.