Question

Create a 4-bit full adder design using VHDL in vivado 2017.2.

Project description: You need to create a vhd file for the four-bit full adder.

Note: Instead of using bit, please use std_logic; instead of using bit_vector, please use std_logic_vector.

One simulation source is required, i.e. testbench

Please don't write out on paper. Code written out in text or screen shots would be very much apprecitated.

Answer 1

andGate.vhd:

ibrary ieee;

use ieee.std_logic_1164.all;

entity andGate is

port( A, B : in std_logic;

F : out std_logic);

end andGate;

architecture func of andGate is

begin

F <= A and B;

end func;

xorGate.vhd:

library ieee;

use ieee.std_logic_1164.all;

entity xorGate is

port( A, B : in std_logic;

F : out std_logic);

end xorGate;

architecture func of xorGate is

begin

F <= A xor B;

end func;

orGate.vhd :

library ieee;

use ieee.std_logic_1164.all;

entity orGate is

port( A, B : in std_logic;

F : out std_logic);

end orGate;

architecture func of orGate is

begin

F <= A or B;

end func;

halfAdder.vhd:

library ieee;

use ieee.std_logic_1164.all;

entity halfAdder is

port( A, B : in std_logic;

sum, Cout : out std_logic);

end halfAdder;

architecture halfAdder of halfAdder is

component andGate is

port( A, B : in std_logic;

F : out std_logic);

end component;

component xorGate is

port( A, B : in std_logic;

F : out std_logic);

end component;

begin

G1 : xorGate port map(A, B, sum);

G2 : andGate port map(A, B, Cout);

end halfAdder;

fullAdder.vhd:

library ieee;

use ieee.std_logic_1164.all;

entity fullAdder is

port( A, B, Cin : in std_logic;

sum, Cout : out std_logic);

end fullAdder;

architecture fullAdder of fullAdder is

component halfAdder is

port( A, B : in std_logic;

sum, Cout : out std_logic);

end component;

component orGate is

port( A, B : in std_logic;

F : out std_logic);

end component;

signal halfTohalf, halfToOr1, halfToOr2: std_logic;

begin

G1: halfAdder port map(A, B, halfTohalf, halfToOr1);

G2: halfAdder port map(halfTohalf, Cin, sum, halfToOr2);

G3: orGate port map(halfToOr1, halfToOr2, Cout);

end fullAdder;

fullAdder_tb.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity fullAdder_tb is
end fullAdder_tb;

architecture tb of fullAdder_tb is

component fullAdder is
port( A, B, Cin : in std_logic;
sum, Cout : out std_logic);
end component;

signal A, B, Cin, sum, Cout : std_logic;

begin
mapping: fullAdder port map(A, B, Cin, sum, Cout);

--concurrent processes
process
begin
Cin <= '0'; wait for 5 ns;
Cin <= '1'; wait for 5 ns;
end process;

process
variable errCnt : integer := 0;
begin

A <= '0';
B <= '1';
wait for 10 ns;
assert(sum = '0') report "Error in Sum" severity error;
assert(Cout = '1') report "Error in Cout" severity error;
if(sum /= '1' or Cout /= '0') then
errCnt := errCnt + 1;
end if;

A <= '1';
B <= '1';
wait for 10 ns;
assert(sum = '1') report "Error in Sum" severity error;
assert(Cout = '1') report "Error in Cout" severity error;
if(sum /= '0' or Cout /= '1') then
errCnt := errCnt + 1;
end if;

A <= '1';
B <= '0';
wait for 10 ns;
assert(sum = '0') report "Error in Sum" severity error;
assert(Cout = '1') report "Error in Cout" severity error;
if(sum /= '1' or Cout /= '0') then
errCnt := errCnt + 1;
end if;

if(errCnt = 0) then
assert false report " Testing is successful as no error occurred " severity note;
else
assert false report "Testing is not successful as errors occurred" severity note;
end if;

end process;
end tb;

configuration cfg_tb of fullAdder_tb is
for tb
end for;
end cfg_tb;