Question

synchronous/preset/reset/clear vs. asynchronous preset/reset/clear

Please explain the difference and the different in VDHL. thank you.

Answer 1

Asynchronous RESET/PRESET

library ieee;

use ieee.std_logic_1164.all;

entity adder1 is
port
(
clk,reset,enable : in STD_LOGIC;
result : out STD_LOGIC_VECTOR (3 downto 0)
);
end counter_universal;

architecture Behavioral of adder1 is
  
signal add1 : unsigned(3 downto 0);   

--(If reset is 1, the add1 is cleared. so here in asynchronous reset, RESET has highest priority over clock)

-- it will not wait for positive edge or negative edge of clock to reset the signal, once if reset is high it clears the -----------signal no matter whether clock is high or low or rising edge or falling edge

--- if preset is used it sets all the signal to 1 which is again independent of clock   

begin

process(clk, reset) --reset in sensitivity list
begin
   if reset = '1' then ---asynchronous reset
    result <= (others => '0');
       elsif rising_edge(clock) then
add1 <= add1+ 1;
end if;
end process;
result<= std_logic_vector(add1);

end Behavioral;

Synchronous RESET/PRESET

library ieee;

use ieee.std_logic_1164.all;
entity adder1 is
port
(
clk,reset,enable : in STD_LOGIC;
result : out STD_LOGIC_VECTOR (3 downto 0)
);
end counter_universal;

architecture Behavioral of adder1 is
  
signal add1 : unsigned(3 downto 0);   
begin

-----clock has highest priority over RESET or PRESET

----even if reset or preset is 1, the circuit will be cleared to 0 or 1 only @ positive edge or negative edge of clock..

----.if for any edge of the clock, if reset or preset is not high and it becomes high after some time where there is no ------clock edge --------then reset or preset will not have any effect on the circuit.

process(clock)

begin
if rising_edge(clk) then
if (reset = '1') --reet has affect only @ positive edge of clock
add1 <= (others => '0');
  
end if;
end process;