Question

The basic pipeline for DLX has five stages IF, ID, MEM, and WB. Assuming all memory access takes 1 clock cycle

What is the control hazard of an instruction pipeline? Provide three branches of prediction alternatives to reduce branch hazard

What is the data forwarding scheme used to reduce the data hazard?

Answer 1

Control hazards may cause performance loss to the DLX pipelines. They can arise from the pipelining of the branches as well as from other instructions which can change the PC.

Here are three branches of prediction alternatives that are used to reduce branch hazard:

• Stall pipeline: this scheme is simple to handle the branches such that it can easily free or freeze the pipeline, deleting or holding any instructions after the branch until branch destination is known.
• Predict taken: this scheme is used to predict the branch as taken. When the branch is decoded and the target address is computed , the branch is taken and fetching and execution starts to begin at target address.
• Predict not taken: this is high performance scheme and used to predict those branch which is not taken. It actually allows hardware to continue as if the branch is still not executed

Data forwarding is the technique where the result is not needed by the SUB instructions until the ADD operation is performed. In data forwarding, the ALU result from the MEM register is always fed back to the input latches of ALU. This is how data hazards can be reduced using this technique.