`timescale 1 ns / 1 ns module cir(a, b, f); input a, b; output f; assignf=...

`timescale 1 ns / 1 ns
module cir(a, b, f); input a, b;
output f;
assignf= ~(a&b);
endmodule
(1). Write a general verilog testbench for the above circuit without using any task. You must include all four testing cases for a and b. module cir_tb;

Expert Solution

code:

output :

raw_code :

`timescale 1ns / 1ns

module cir_tb();
reg a,b;
wire f; //declaring output as reg

cir c(a,b,f); //instantiation

initial
$monitor("a = %b, b = %b , f= %b",a,b,f); //displaying in td console

initial
begin
//testing for all four cases
a = 1'b0;b = 1'b0; #20;
a = 1'b0;b = 1'b1; #20;
a = 1'b1;b = 1'b0; #20;
a = 1'b1;b = 1'b1;
end
endmodule

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venereology answered 6 months ago

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