Question

Design a memory management scheme for a 48 bit architecture, using various types of paging and/or segmentation. You should include a clear translation scheme from a 48 bit logical address to a 48 bit physical address including a picture that shows this translation procedure. Then highlight its advantages and disadvantages.

Answer 1

Logical address includes :

1. Page number denoted by p: bits required to represent page in logical address space.
2. Page offset denoted by d: bits required to represent word in a page.

Physical address includes:

1. Frame number denoted by f: bits required to represent frame in physical address space.
2. Frame offset denoted by d: bits required to represent a word in a frame.

here, logical address is 48 bits, then logical address space is = 2⁴⁸ words

logical address = log₂ 2⁴⁸ bits = 48 bits

assuming both frame and page size is 16k, we get number of pages = 2⁴⁸/16k = 2³⁴

advantage:

1. its more efficient if implement in hardware.
2. allows OS to implement memory scheme in hardware, instead of software

disadvantage:

1. in worst case, translation could take long time due to multiple table lookup.
2. cache miss is present.