a)In applying pull up and pull down principle, demonstrating all steps and in your own
understanding use Y = A +{ B × ( C +D ) } to DESIGN four input CMOS Static logic gate
.

b) In your own understanding in the field of electronics analyze the advantages of BJT
over MOSFET?

c ). In your level of understanding, explain the importance of biasing a transistor in a given
working electronic Circuit. Explain also the consequence when such transistor does not
biases properly

Explain how a shift register may be used to expand the output capabilities of a processor when only utilising a few pins

From the construction point of view, enumerate the common essential features of rotating electrical machines.

Please answer the following questions in "Energy Efficiency Basics" multiple choice:

QUESTION 7
An electrical system has 52.9 kVA and 50.5 kW. How many kVARs of capacitance are required to correct the power factor of the total load to 95%? a. 10.8 kVARs
a 0 kVARs
b 20 kVARs
c 35 kVARs
d 75 kVARs

QUESTION 8
You find that you can replace a 50 kW motor with a 5 kW motor by cutting the total air flow requirements, given than ( motor running time is 8,750 hours/year, efficiency 90% for both motors, demand charge $ 9 /kW-month, energy charge $0.05/kWh fuel adjustment cost $0.005/kwh). Calculate the dollar savings ?
a $ 29,490
b $20,400
c $22,090
d $14,010

QUESTION 9
An air handler delivers 1,200 L/s of air at 10 ºC. When the air arrives at the space to be cooled, it is 20 ºC. How many kW of air conditioning capacity has been lost?
a 6 kW
b 14.4 kW
c 12.1 kW
d 20 kW

QUESTION 10
If a 75-kW fan motor has a VSD installed that slows down the fan by 20% what is the effect on air flow rate and the kW savings?
a 20% CFM reduction, and 36.6 kW savings
b 80% CFM reduction, and 51.2 kW savings
c 20% CFM reduction, and 20 kW savings
d 20% CFM reduction, and 37.4 kW savings

QUESTION 11
In a given facility you measure the incoming supply 3 phase voltage and you find the following voltages present. 236V 231V 227V. What impact is this likely to have on the motor load in the installation? imbalance?
a Increase motor losses by approx. 7%
b Increase motor losses by approx. 15%
c Reduce motor losses by approx. 7%
d Reduce motor losses by approx. 15%

Verilog code to make 8bit bcd to 8bit binary please

with testbench

1. How can buffer overflows be avoided and what are the steps involved in a buffer overflow exploit?

2. What are some of the C functions susceptible to buffer overflow?

Given a Boolean function: f(a,b,c,d) = m(1,6,7,10,12)+dc(3,4,9,15). i) Design a circuit for implementing f(a,b,c,d) with ONE 4-to-1 MUX and other basic logic gates. USE a and b as select inputs. ii) Draw the circuit. iii) Write the VHDL code for a 4-to-1 MUX, named “mux_4to1”, with input: a, b, c, d, s0, s1; and output: z. iv) Write the complete VHDL code for the above circuit in part (iii), named “Boolean_MUX”.

Starting from the dynamic equations of the PM DC motor obtain the voltage-to-speed transfer function in s-domain. Draw the block diagram.

Design an analog-digital converter circuit with OpAmp that receives a 5 Vp sinusoidal signal and a 3.5 V trip level as input. It must deliver a TTL (Low / High) signal as output.

Please answer the following questions (Show procedure) .... Thank you.

1. Calculate the cutoff frequency of an active first order low-pass filter with an R1 = 12kOhm and C1 = 0.02 uF.

2. Calculate the cutoff frequencies of a bandpass filter circuit with R = 10 kOhm, C1 = 0.1 uF and C2 = 0.002 uF.

A 480 V, 50 Hz, Y-connected six-pole synchronous generator has a per-phase synchronous reactance of 1.0
Ω. Its full-load armature current is 60 A at 0.8 PF lagging. Its friction and windage losses are 1.5 kW and
core losses are 1.0 kW at 60 Hz at full load. Assume that the armature resistance (and, therefore, the I2R
losses) can be ignored. The field current has been adjusted such that the no-load terminal voltage is 480 V.
a. What is the speed of rotation of this generator?
b. What is the terminal voltage of the generator if :

c. What is the efficiency of this generator (ignoring the unknown electrical losses) when it is operating
at the rated current and 0.8 PF lagging?
d. How much shaft torque must be applied by the prime mover at the full load? how large is the induced
counter-torque?
e. What is the voltage regulation of this generator at
i. 0.8 PF lagging ii. at Unity PF iii. at 0.8 PF leading?
a. The figure below is a set of Synchronous Generator and Synchronous Motor. The ratings of the
machines are as follows:
Synchronous Generator: . 3ph, 1.0 MVA, 2.3kV, 50Hz, 0.85 lagging power factor, Xs =0.9 pu
Synchronous Motor: 3ph, 0.5 MVA, 2.3kV, 50Hz, 0.85 leading power factor, Xs =0.8 pu
The generator is equipped with a voltage regulator which maintains the terminal voltage at the rated value.
The motor delivers 500 hp and it field current is adjusted to make it operate at unity power factor.

a. The figure below is a set of Synchronous Generator and Synchronous Motor. The ratings of the
machines are as follows:
Synchronous Generator: . 3ph, 1.0 MVA, 2.3kV, 50Hz, 0.85 lagging power factor, Xs =0.9 pu
Synchronous Motor: 3ph, 0.5 MVA, 2.3kV, 50Hz, 0.85 leading power factor, Xs =0.8 pu
The generator is equipped with a voltage regulator which maintains the terminal voltage at the rated value.
The motor delivers 500 hp and it field current is adjusted to make it operate at unity power factor.

The following test results are obtained for a 3ph, 25 kV, 750 MVA, 50 Hz, 3600rpm, star-connected
synchronous machines at rated speed.

If=1500A VLL(Open circuit)=25KV, IA(open circuit test)=10000A,VLL(air gap line)=30KV

g. Calculate the capacitance of a square parallel plate capacitor having two
dielectrics εr1=2.5 and εr2=3.5 each comprising one half of the area between
the plates. The area of a plate is 4.0 x 104 cm2 and the two plates separated by
a distance of 20mm.
h. If a 24V volts electric potential is applied across the terminals of this
capacitor described above, find the electric potential energy stored in the
capacitor.

please answer these for me

Suggest two techniques to compensate the effect of distance between the sensor and forehead on the accuracy of IR temperature sensor and
Design an experiment setup for determination the time constant of a thermistor?

What cause the main transient response of the system.

• A. Dominant roots

• B. Locus

• C. Asymptote centroid

• D. Auxiliary polynomial

Design a 3-bit 2’s complement adder/subtractor with overflow flag detection

Design and simulate a structural model (not behavioral) of a 3-bit Adder/Subtractor). Use the 3-bit carry propagate adder of the project as a module for your adder/subtractor. The inputs A and B should be positive binary numbers where vector B must be converted to a negative 2's complement when a subtraction operation is configured. When m=0 it should perform and addition (A+B) and if m=1 it should perform a subtraction operation (A-B)

Your module ports (inputs and outputs), should be as follow:

module add_sub(

   input [2:0] a, b,

   input m,   // m=0 => addition (a+b);   m=1 => subtraction (a-b)

   output [2:0] result,  

   output overflow

);

/* your wire declarations, n-bit adder and xor gates

go in this section */

endmodule

Create a test bench to test the following 2’s complement cases:

a = 3’b001 b = 3’b001 m = 1’b0     // (1+1=2) => result = 3’b010;  overflow = 1’b0

a = 3’b011 b = 3’b010 m = 1’b1   // (3-2=1) => result = 3’b001;   overflow = 1’b0  

a = 3’b011 b = 3’b010 m = 1’b0     // (3+2=5) =>  result = 3’b101;  overflow = 1’b1   Overflow Error!

a = 3’b110 b = 3’b101 m = 1’b0     // (-2-3)=-5) => result = 3’b011; overflow = 1’b1   Overflow Error!

Your Testbench should clearly display the inputs and output results

=============full_adder.v====================

//full_adder.v

module full_adder
(
input a,b,ci,
output s, co
);

wire w1, w2, w3;

xor x1(w1, a, b);
xor x2(s, w1, ci);
nand n1(w2, w1, ci);
nand n2(w3, a, b);
nand n3(co, w2, w3);

endmodule

Two cables, both with conductor cross-sectional area 6 mm2, are connected in parallel across a common D.C. voltage of 21 Volts.

The resistivity of Cable 1 is ρ = 2.0 x 10-9 Ω.m at 20 °C, while the resistivity of Cable 2 is ρ = 3.0 x 10-9 Ω.m at 20 °C.

Cable 1 is 1348 mm in length.

If 43.2 % of the current passes through cable 1, determine the length of cable 2.

Assume the ambient temperature is 20°C