Question

Given a Boolean function: f(a,b,c,d) = m(1,6,7,10,12)+dc(3,4,9,15). i) Design a circuit for implementing f(a,b,c,d) with ONE 4-to-1 MUX and other basic logic gates. USE a and b as select inputs. ii) Draw the circuit. iii) Write the VHDL code for a 4-to-1 MUX, named “mux_4to1”, with input: a, b, c, d, s0, s1; and output: z. iv) Write the complete VHDL code for the above circuit in part (iii), named “Boolean_MUX”.

Answer 1

--4to 1 mux VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_4to1 is
port(

a,b,c,d : in STD_LOGIC;
s0,s1: in STD_LOGIC;
z: out STD_LOGIC
);
end mux_4to1;

architecture behavioral of mux_4to1 is
begin
process (a,b,c,d,s0,s1) is
begin
if (s0 ='0' and s1 = '0') then
z <= a;
elsif (s0 ='1' and s1 = '0') then
z <= b;
elsif (s0 ='0' and s1 = '1') then
z <= c;
else
z <= d;
end if;

end process;
end behavioral;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY boolean_mux IS
port(
a,b,c,d : in STD_LOGIC;
f: out STD_LOGIC
);
END boolean_mux;

ARCHITECTURE behavior OF boolean_mux IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mux_4to1
PORT(
a,b,c,d : in STD_LOGIC;
s0,s1: in STD_LOGIC;
z: out STD_LOGIC
);
END COMPONENT;

--Inputs
signal d0 : std_logic;
signal d1 : std_logic ;
signal d2 : std_logic ;
signal d3 : std_logic ;
  

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: mux_4to1 PORT MAP (
a => d0,
b => d1,
c => d2,
d => d3,
s0 => a,
s1 => b,
z => f
);

-- Stimulus process
process (a,b,c,d)
begin
d0 <= d ;
d1 <= c or (not d);
d2 <= c xor d;
d3 <= not d2 ;
  

end process;

END;