Question

Design a 3-bit 2’s complement adder/subtractor with overflow flag detection

Design and simulate a structural model (not behavioral) of a 3-bit Adder/Subtractor). Use the 3-bit carry propagate adder of the project as a module for your adder/subtractor. The inputs A and B should be positive binary numbers where vector B must be converted to a negative 2's complement when a subtraction operation is configured. When m=0 it should perform and addition (A+B) and if m=1 it should perform a subtraction operation (A-B)

Your module ports (inputs and outputs), should be as follow:

module add_sub(

   input [2:0] a, b,

   input m,   // m=0 => addition (a+b);   m=1 => subtraction (a-b)

   output [2:0] result,  

   output overflow

);

/* your wire declarations, n-bit adder and xor gates

go in this section */

endmodule

Create a test bench to test the following 2’s complement cases:

a = 3’b001 b = 3’b001 m = 1’b0     // (1+1=2) => result = 3’b010;  overflow = 1’b0

a = 3’b011 b = 3’b010 m = 1’b1   // (3-2=1) => result = 3’b001;   overflow = 1’b0  

a = 3’b011 b = 3’b010 m = 1’b0     // (3+2=5) =>  result = 3’b101;  overflow = 1’b1   Overflow Error!

a = 3’b110 b = 3’b101 m = 1’b0     // (-2-3)=-5) => result = 3’b011; overflow = 1’b1   Overflow Error!

Your Testbench should clearly display the inputs and output results

=============full_adder.v====================

//full_adder.v

module full_adder
(
input a,b,ci,
output s, co
);

wire w1, w2, w3;

xor x1(w1, a, b);
xor x2(s, w1, ci);
nand n1(w2, w1, ci);
nand n2(w3, a, b);
nand n3(co, w2, w3);

endmodule

Answer 1

//verilog module

module add_sub(a,b,m,result,overflow);

input[2:0]a,b;
input m;
  
output [2:0]result;
  
output overflow;
  
wire [2:0]temp;
wire [2:0]t_c;
  
xor n1(temp[2],b[2],m);
xor n2(temp[1],b[1],m);
xor n3(temp[0],b[0],m);

// Full after instance given is used

full_adder n4(a[0],temp[0],m,result[0],t_c[0]);
full_adder n5(a[1],temp[1],t_c[0],result[1],t_c[1]);
full_adder n6(a[2],temp[2],t_c[1],result[2],t_c[2]);

xor n7(overflow,t_c[2],t_c[1]);
  
endmodule

//full adder instance module

module full_adder
(
input a,b,ci,
output s, co
);

wire w1, w2, w3;

xor x1(w1, a, b);
xor x2(s, w1, ci);
nand n1(w2, w1, ci);
nand n2(w3, a, b);
nand n3(co, w2, w3);

endmodule

//testbench

module test;

reg [2:0]a,b;
reg m;
  
wire [2:0] result;
wire overflow;
  
add_sub dut (a,b,m,result,overflow);
  
initial
begin
$dumpfile("var.vcd");
$dumpvars;
a=3'b001;b=3'b001;m=1'b0;#30;//(1+1=2)=> result=3'b010; overflow=1'b0
a=3'b011;b=3'b010;m=1'b1;#30;//(3-2=1)=> result=3'b001;overflow=1'b0
a=3'b011;b=3'b010;m=1'b0;#30;//(3+2=5)=> result=3'101;overflow=1'b1 overflow Error
a=3'b110;b=3'b101;m=1'b0;#30;//(-2-3=-5)=> result=3'b011;overflow=1'b1 overflow Error
$finish;
  
end
endmodule

Simulated waveform