4. Explain Over- Current Protection Concepts in detail.

The real ammeter (with 0 resistance) and voltmeter (with infinity resistance) do not achieve ideal values (When using in a lab), but can behave as "effectively ideal" under some conditions. what are those conditions? and what are the approximate value of resistances of the meters that normally use in labs?

Choose the correct answer from the followings:

a) In Wheatstone bridge, when it is balanced the galvanometer reads

1. Infinity 2. Zero 3. 5 mA 4. 10 mA
b) In PMMC, dumping force helps .............

1. To move the pointer to read our measurements correctly 2. To reset our readings back to zero 3. To stabilize the pointer during transition between readings 4. All the above
c) A current transformers are used for:

1. For cost effective measurement 2. For protections 3. To reduce the cost of relay and circuit-breaker in high current enviroemnt 4. All the above

The contribution densities of a Si pn joint polarized in the direction of transmission at T = 300K are Nd = 4 * 10 ^ 15 cm ^ -3, Na = 8 * 10 ^ 17 cm ^ -3. The minority carrier hole concentration at the border of the space charge zone is given as pn (xn) = 14 * 10 ^ 13 cm ^ -3. According to other parameters of the pn junction tau n0 = 0.2 microseconds, tau p0 = 0.5 microseconds, A = 2.5 mm ^ 2, Dn = 25 (cm ^ 2 / s), Dp = 10 (cm ^ 2 / s):

a) Pole voltage Va in the direction of transmission,
b) minority carrier hole diffusion current in x = xn,
c) minority carrier hole diffusion current in x = xn + 2Lp,
d) Electron concentration in x = -xp,
e) minority carrier electron diffusion current in x = -xp,
f) minority carrier electron diffusion current in x = - (xp + 3Ln),
g) Calculate the total current flowing through the junction.

I need quick answer pls.Thank you.

Why are we designed to have different BJT amplifier? Write titles and The use (Benefits and drawbacks)

Topic: Introduction to Convolution

Software used : Matlab

Course : Signal and Systems Lab

1.

a) Make the flowchart or pseudo code for convolution.

b) Implement convolution in MATLAB.

   Hint: Make a function using the format: function result = myconv (a,b)

            Where a and b are input matrix and result is convolution answer.

c) Compare it with conv command.

2. Let input signal x be [1, 3, –2, 4, -1] and the system h be [-2, 3, 4, –3, 6]. Find the output of the system y using the conv command.

3. Now suppose we add another system j = [3, –1, 2, 4, 1] in series with the above system. Now find the overall response and output y of the above system using the conv command. Hint: The systems h and j should be convolved first and then the resultant should be convolved with x to get the overall response.

4. Again suppose now j is attached in parallel to h. Now find the impulse response y for the system.

5. Now suppose the two systems h and j are again in series and a third system k = [2, 3, 4, 5, 6] has also been attached with them in parallel. Find the impulse response of the overall system and hence the output y. Hint: You will have to make sure that the size of the system k be made equal to the resultant of the size of the system obtained by convolving the systems h and k that are attached in series.

Up until now we have supposed that all signals starting point is same say 0. Now suppose the system h starting point is –2, that of system j is 0 and that of system k is 3. Now handle this situation carefully and get the overall impulse response of the system and hence the output y. Also please draw stem plot of each of system including the input x, systems, h, j, k, the overall response and finally the output y.

6. Write a program without using conv command and for loop to convolve two arbitrary length signals. (Hint: Use toeplitz command)  

Can someone run this in vhdl and send me the output? acreenshot

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity VHDL_MOORE_FSM_Sequence_Detector is
port (
 clock: in std_logic; --- clock signal
 reset: in std_logic; -- reset input
 sequence_in: in std_logic; -- binary sequence input
 detector_out: out std_logic -- output of the VHDL sequence detector
);
end VHDL_MOORE_FSM_Sequence_Detector;

architecture Behavioral of VHDL_MOORE_FSM_Sequence_Detector is
type MOORE_FSM is (Zero, One, OneZero, OneZeroZero, OneZeroZeroOne);
signal current_state, next_state: MOORE_FSM;

begin
-- Sequential memory of the VHDL MOORE FSM Sequence Detector
process(clock,reset)
begin
 if(reset='1') then
  current_state <= Zero;
 elsif(rising_edge(clock)) then
  current_state <= next_state;
 end if;
end process;
-- Next state logic of the VHDL MOORE FSM Sequence Detector
-- Combinational logic
process(current_state,sequence_in)
begin
 case(current_state) is
 when Zero =>
  if(sequence_in='1') then
   -- "1"
   next_state <= One;
  else
   next_state <= Zero;
  end if;
 when One =>
  if(sequence_in='0') then
   -- "10"
   next_state <= OneZero;
  else
   next_state <= One;
  end if;  
 when OneZero => 
  if(sequence_in='0') then
   -- "100"
   next_state <= OneZeroZero;
  else
   next_state <= One;
  end if;  
 when OneZeroZero =>
  if(sequence_in='1') then
   -- "1001"
   next_state <= OneZeroZeroOne;
  else
   next_state <= Zero;
  end if; 
 when OneZeroZeroOne =>
  if(sequence_in='1') then
   next_state <= One;
  else
   next_state <= OneZero;
  end if;
 end case;
end process;
-- Output logic of the VHDL MOORE FSM Sequence Detector
process(current_state)
begin 
 case current_state is
 when Zero =>
  detector_out <= '0';
 when One =>
  detector_out <= '0'; 
 when OneZero => 
  detector_out <= '0'; 
 when OneZeroZero =>
  detector_out <= '0'; 
 when OneZeroZeroOne =>
  detector_out <= '1';
 end case;
end process;
end Behavioral;

TESTBENCH-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY tb_VHDL_Moore_FSM_Sequence_Detector IS
END tb_VHDL_Moore_FSM_Sequence_Detector;
 
ARCHITECTURE behavior OF tb_VHDL_Moore_FSM_Sequence_Detector IS 
 
    -- Component Declaration for the Moore FSM Sequence Detector in VHDL
 
    COMPONENT VHDL_MOORE_FSM_Sequence_Detector
    PORT(
         clock : IN  std_logic;
         reset : IN  std_logic;
         sequence_in : IN  std_logic;
         detector_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clock : std_logic := '0';
   signal reset : std_logic := '0';
   signal sequence_in : std_logic := '0';

  --Outputs
   signal detector_out : std_logic;

   -- Clock period definitions
   constant clock_period : time := 10 ns;
 
BEGIN
 
 -- Instantiate the Moore FSM Sequence Detector in VHDL
   uut: VHDL_MOORE_FSM_Sequence_Detector PORT MAP (
          clock => clock,
          reset => reset,
          sequence_in => sequence_in,
          detector_out => detector_out
        );

   -- Clock process definitions
   clock_process :process
   begin
  clock <= '0';
  wait for clock_period/2;
  clock <= '1';
  wait for clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin  
      -- hold reset state for 100 ns.
  sequence_in <= '0';
  reset <= '1';
  -- Wait 100 ns for global reset to finish
  wait for 30 ns;
      reset <= '0';
  wait for 40 ns;
  sequence_in <= '1';
  wait for 10 ns;
  sequence_in <= '0';
  wait for 10 ns;
  sequence_in <= '1'; 
  wait for 20 ns;
  sequence_in <= '0'; 
  wait for 20 ns;
  sequence_in <= '1'; 
  wait for 20 ns;
  sequence_in <= '0'; 
      -- insert stimulus here 
      wait;
   end process;

END;

Assuming a characteristic impedance of 75 Ω and a load impedance of 100Ω, find the input
impedance at λ/2, λ and 2λ. How each input impedance will vary for the case of: i) matched
line; ii) short-circuit line; iii) open circuit line?

Draw the circuit diagram of a stand-alone photovoltaic system assisted with batteries and explain the function of each stage of the system.

write gate level 4bit carry look ahead adder in verilog without any assign and always in the code.

Why do we need the assumption of AC signal to be a small signal for amplifier analysis?

Alice and Bob setup an elliptic curve Diffie-Hellman key exchange protocol with thesame field, curveEand pointPas given in Problem 1.Suppose that Alice selected random numbera= 3and Bob selectedb= 4, show the stepsperformed by Alice and Bob to obtain their shared key. What isthe key?