Determine the most economical size of a 3-phase line which supplies the following loads at 10 kV : (i) 100 kW at 0·8 p.f. (lag) for 10 hours (ii) 500 kW at 0·9 p.f. (lag) for 8 hours (iii) 100 kW at unity p.f. for 6 hours. The above gives the daily load cycle. The cost per km of the completely erected line is Rs (8000 a + 1500) where a is the area of cross-section of each conductor. The combined interest and depreciation is 10% per annum of capital cost. Cost of energy losses is 5 paise per kWh. Resistivity of conductor material = 1·72 × 10−6 Ω cm.

(A) Minimize the following Boolean expression as much as possible and Design the obtained function with NAND universal logic gates
Y = AB + A(B+C) + B (B+C)

(B) Design a logic gate circuit diagram ( combination circuit ) that accepts a 3 - bit BCD number and generates an output binary number equal to the square of input number.

You are to design two CONCEPUTALLY different synchronous state machines (Mealy and Moore) that perform the task described below. You are allowed to use any type of flip-flop. However, I recommend that you use either JK or D flip-flops. There is a game called screwball. Every time a ball is put into play either player 1 (P1) scores a point or player 2 (P2) scores a point. A winner is declared when one player is ahead by 2 points. Starting with a score of 0:0 for P1 vs. P2, a game might progress as follows: 0:1 1:1 2:1 3:1 (P1 Wins!) Design a finite state machine that uses information about which player scores a point at each stage of a game to determine when a player wins and which player wins. Your design should include one reset input to initialize your win announcer (this may be a synchronous or an asynchronous input, as you desire). The outputs from your designs should indicate BOTH when a win has occurred and which player is the winner. Hint: You design should have one input (Ball) and two outputs (Player 1 (P1) and Player 2 (P2))

Please Use Mealy State. Thank You!

What would be the wiring setup and coding using an Arduino for a display of the temperature of the room it is in?

Describe briefly with the aid of suitable diagrams the mechanism of the lightning
stroke generation.

8. What two circuits are used to generate the IF? (Intermediate Frequency)

62. The synthesizer in a transceiver usually generates what
frequencies?

Need explanation of MATLAB code which creates echo. (SIGNAL PROCESSING)

If the original audio signal is x(t) then the echo is y(t) = x(t) + alpha*x(t-delay)

This code below creates this echo however I don't understand how every line of the code works, could someone comment this code so I can understand?

[x,Fs] = audioread('Hallelujah.wav');  
 sound(x,Fs);   
 delay = 0.5; % 0.5s delay  
 alpha = 0.65; % echo strength  
 D = delay*Fs;  
 y = zeros(size(x));  
 y(1:D) = x(1:D);  
   
 for i=D+1:length(x)  
   y(i) = x(i) + alpha*x(i-D);  
 end  

a.) Define constant power load (CPL) and constant voltage load (CVL). Are power electronics devices constant power loads? If so, explain why.

b) How can Zener diodes work as voltage stabilizer?

c) Mention the typical value of resistance (Ohm-m) and conductance (Siemens/meter) for conductors, semiconductors and insulators.

4. Bit sequence recognizer [30]

• Submission file for this part: 4.circ
• Main circuit name: sequencecheck
• Input pin(s): inputx [1], sysclock [1]
• Output pin(s): outputr [1]

Derive a minimal state table for a Mealy model FSM that acts as a sequence checker. During four consecutive clock cycles, a sequence of four values of the signal x is applied, forming a binary number. The oldest value of x would become the most significant bit in that binary number. The most recent value of x would become the least significant bit.

The FSM will output outputr = 1 when it detects that the previous 4 bit sequence was either 0100 or 1010. At all other times, including when the previous sequence was not those described previously, outputr = 0. Implement the FSM as a circuit in Logisim Evolution.

Note that much like the last problem, this is not a sliding window. After the fourth clock pulse, the circuit resets itself and is ready to take in the next 4 bit sequence.

You will lose a significant portion of credit if your FSM is not minimized.

You will lose a significant portion of credit if your combinational logic is not minimized. If you violate both this and the previous constraint, you will get a 0

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS. show the some simulation results .

a full elaborate explanation on the theory behind induction type Instruments including calculations pertaining to them

mathematical derivations

a)The voltage and the current of a circuit are v=1∠30^oV and i=2∠-37^oA. Determine the power factor.

b)A short transmission line is delivering a 3-phase load of 1MVA at 11kV and the load power factor is 0.8 lagging. The total series impedance of the line is (10 + j20)Ω/phase. Calculate the sending end power factor.

c)A supply company offers a Two-parts Tariff on a monthly basis. The Maximum Demand Charge is $90 per kVA per month and the Energy Charge is $0.6 per kWh. A factory has a load of average 200kW. It operates at a monthly load factor of 0.75 and a power factor of 0.85 lagging. Assume the factory works 400 hours per month, determine the electricity charge.

d)Two generators G1 and G2 are connected in parallel to an 11kV common busbar. The generator G1 is rated at 15MVA, 11kV with X=0.10pu and the generator G2 is rated at 10MVA, 11kV with X=0.10pu. The 11kV busbar feeds an 11/66kV, 15MVA, X=0.06pu step-up transformer. Calculate the fault current when a three phase fault occurs on the high voltage side of the transformer. Select 15MVA as the base power.

Explanation of lenz's law and other electromagnetic theorems and it's relation to induction type instruments

Estimate the desired parameters and draw the block diagram of an Armstrong indirect FM modulator to generate an FM carrier with a carrier frequency of 102 MHz and ∆? = 25 kHz based on following constraint: (1) A narrow-band FM generator is available at a carrier frequency 200 KHz and ∆? is 12.2 Hz.( 2) The local oscillator has an adjustable range of 9 MHz to 10 MHz. (3) There is bandpass filter with any center frequency. (4) And only doublers are available.

How do an Electrical Engineering student need Calculus II ? Find an Application that relates to Electrical Engineering?