Explain about three-phase resonant converters ?

1. Given    V=100V    R=10kΩ    C=10µF    (10 pts)

1. Determine the mathematical expression for v_c

2. Determine the mathematical expression for i_c

3. Computer the capacitor voltage at t=150 ms

4. Computer the capacitor current at t=150 ms

5. Locate the points on the voltage and current curves.

Plot the effect of proportional (Kp), integral (Ki), and derivative (Kd) gains to a step-change in an error signal, e(t). At least make three plots (1-3), each containing three graphs:

1. Graph 1 High Kp; graph2: medium Kp; graph 3: low Kp

2. Graph 1: Low Kd; Graph 2: medium Kd; Graph 3: high Kd

3. Graph 1: High Kp and Ki; Graph 2: medium Kp, Ki, and Kd; Graph 3: low Kp and Ki

If you're not answering all three parts of this question, don't answer it.

Consider the following FSM VHDL code:

library ieee;

use ieee.numeric_std.all;

entity fsm is

port (clock, input, reset: in std_logic;

output: out std_logic_vector (2 downto 0));

end;

architecture bhv of fsm is

type state is (s1, s2, s3, s4);

signal sreg: state;

begin

sreg_machine: process (clock)

begin

if (reset='1') then

sreg <= s1;

output <= "000";

elsif (rising_edge(clk)) then

case sreg is

when s1=>

output <= "000";

if (input='0') then

sreg <= s2;

else

sreg <= s1;

end if;

when s2=>

output <= "010";

if (input='1') then

sreg <= s4;

else

sreg <= s3;

end if;

when s3=>

output <= "100";

if (input='0') then

sreg <= s1;

else

sreg <= s4;

end if;

when s4=>

output <= "101";

if (input='0') then

sreg <= s4;

else

sreg <= s3;

end if;

end case;

end if;

end process;

end architecture;

a) Draw the state diagram for this FSM.

b) What kind of FSM is this? Mealy or Moore? Why?

c) Do you see issues with this FSM VHDL code for simulation or synthesis? List your answers (if any) and explain how you fix the coding issue.

(a) Explain the principle of transformer action.
(b) Derive an expression for the e.m.f. induced in a transformer winding. Show that emf per turn in primary is equal to e.m.f. per turn in the secondary.

Six poles, 60 [Hz], and three super-executive induction motors have total load revolutions of 1,050 [rpm]. In order to rotate it to 1000 rpm on the same torque, determine what external resistance [ohm] should be inserted into the secondary side. However, the second side has r2 resistance in the Y duel.

A factory need a drive system for a conveyer system. Voltage source available is three phase 415
Volt, 50 Hz. Electric motor that they use is DC motor.
(i) How the design of DC drive system for that system :
(ii) What the parameters should be considered?
(iii) What type of the DC motor that needed?
(iv) What kind of converters that suitable for this system?
(v) How the control system?

Write VHDL code (behavior model) to implement a 4-bit modulo-9 counter and simulate your VHDL code of 4-bit modulo-9 counter in ModelSim, and capture the screenshot

of your simulated waveform.

Assume clock period Tclk=100ns, initially, the counter is reset to Q₃Q₂Q₁Q₀=0000 you need to simulate a complete counting cycle plus one more additional clock period after it is reset to “0000” state.

Design a 4-to-1 multiplexer using VHDL

a- use with-select-when statement in writing VHDL file

generate timing diagram

QUIESTION 1
A three-phase synchronous generator is connected to an infinite bus. The infinite bus voltage and the generated voltage are o 1.0 pu ∠0 and o 1.0pu ∠42.84 , respectively. The synchronous reactance is 0.85 pu and resistances are neglected. a) Compute power angle (δ), armature current (Is), power factor (pf), real power (P), and reactive power (Q). Draw the phasor diagram. b) If the prime mover torque is kept constant at a value corresponding to P=0.8 pu, compute the required value of the generated voltage (E2) for the unity power factor condition (and constant power, P=0.8 pu). What is the new value of power angle (δ2)? Solution: δ= 42.84o , Is = 0.86pu ∠21.44o , pf=0.93, P=0.8 ph, Q= -0.314pu, δ2 = 34.2o , E2= 1.21pu

QUESTION 2
Two “three-phase Y-connected synchronous generators” have per phase generated voltages of o 1 E = 120 V∠10 and o 2 E = 120 V∠20 under no load, and resistance of X j5 Ω / phase 1 = and X j8 Ω / phase 2 = . They are connected in parallel to a load impedance of XL = 4 + j3 Ω / phase . Compute: a) Per phase terminal voltage Vt (both magnitude and phase angle). b) Armature currents for each generator ( a1 a2 I and I ). c) Power supplied by each generator (P1 and P2 ). d) The total output power (Pout ). Solution: Vt= 82 V ∠-5.94o , Ia1 = 9.36 A ∠-51.17o , Ia2 = 7.31 A ∠-32.06o , P1 = 1621 W, P2 = 1614.5 W, Pout = 3236 W.

Draw a PLC ladder logic diagram to simulate the operation of a sequential taillight system. The light system consists of three separate lights on each side of the car. Each set of lights will be activated separately, by either the left or right turn signal switch. There is to be a 1-s delay between the activation of each light, and a 1-s period when all the lights are off. Ensure that when both switches are on, the system will not operate. Use the least number of timers possible. The sequence of operation should be as follows:

• The switch is operated.

• Light 1 is illuminated.

• Light 2 is illuminated 1 s later.

• Light 3 is illuminated 1 s later.

• Light 3 is illuminated for 1 s.

• All lights are off for 1 s.

• The system repeats while the switch is on

3. For the following analog signal: xa(t) = 3sin(40πt) + 3cos(50πt) which is sampled at a rate of 100 samples/second. a. Design an IIR digital filter that will pass the first component 3sin(40πt) with attenuation of less than 1 dB and suppress the second component 3cos(50πt) at least 50 dB. The filter should be monotonic in the passband and have ripple in the stopband. ( 2 points ) b. Generate 500 samples of the sampled signal xa(t) at the given sampling rate and use the filter you designed to process the sampled signal using MATLAB’s ”filter” command. ( 1 point ) c. Plot the original signal and the output signal in one window using MATLAB’s subplot command ( in either a 1 X 2 arrangement or a 2 X 1 arrangement. Remember to title all plots and label all axes.

PLEASE SOLVE USING MATLAB

Could you drive full-substractor for 1 bit . Could you use nand,nor,inverter,or gate. Those gate should combine our circuit.You can not use other gate. Thank you for support.

Note: Draw the schematic and code for each of the following question. All question carries equal marks.

1. Design heat control system as follow.

Design a system to maintain the temperature of the system at 37 degree celcius.A temperature sensor is attached with the Arduino analog input. A fan (220 volts) and heater (220V) is placed in a room. If temperature is greater than 37 degree, turn the fan on and if temperature is less than 37 turn on heater.

Take the temperature reading after every 10 minutes.

*Hint: Use relay to turn on Fan and heater.Control the realy using Arduino.