can i use port mapping inside a process in vhdl coding

List the Electric equipment used in Testing and Maintenance of Motors. Discuss each equipment.

1. Differentiate between centralized and distributed generation system.

The Ethernet standard uses CSMA/CD as a MAC protocol, whereas the WiFi networks uses
CSMA/CA. Consider you are using your Home LAN mostly for transferring streaming media
such as video, audio, and playing online games. Analyze your knowledge of medium access
control protocols and point out which protocol would you use? Do justify ?

Q) Implement Buck Converter in PSPICE Orcad. Kindly Perform step by step solution to tool work and version too. thank you

Use Matlab to do the following (please) :

1. Plot the following signals in one figure window using Matlab commands. Given x (n) = {5,2,1,3,1,4,2} plot x(3n)

2. Plot all transformations of a Gaussian signal in one figure window

3. Plot r(-3t-9).

A3)

i) To double the width of a reverse-biased pn junction, should the external voltage be doubled?

ii) To reduce the width of a reverse-biased pn junction,should the external be reduced by half as well?

iii) What is the diffusion lengths of a pn junction?

iv) Show the width of a pn junction is a non linear function of the voltage across the pn junction.

A binary counter has one input X and counts as follows. If X = 0, it counts 2, 3, 1 and repeats; if X = 1, it counts 1, 0, 3 and repeats. You can assume that the following cases do not occur: counter value is 0 with X = 0, and counter value is 2 with X = 1.

(a) Draw the state diagram of the binary counter above. Use the binary counting values as the state names. You do not need to represent the state transitions for the cases that do not occur.

(b) Use two D-type flip-flops and logic gates to design the binary counter. In your answers, include the state table, the flip-flop input equations and the final logic circuit diagram.

Write a matlab code for given task

Use your ‘sin’ or ‘cos’ function to generate a sinusoid wave having two components as
f1 = 3kHz and f2 = 5kHz and then sample it with fs = 10kHz. Calculate its fft with zero frequency
component in the middle. Plot it on a properly scaled w-axis. Specify if there is aliasing or not?
If there is aliasing specify which component is casing the aliasing

A coreless Dc motor is attached with a whell.Generate its tranfer fucntion and kinametis with proper book refrence page(Introduction to robotics) and solution.

Conceptualize the cut off region and a saturation region of a BJT.

A three phase, 60 Hz, 480 V, Y-connected, two-pole synchronous generator has a synchronous reactance of 0.95 Ω per phase. Its armature resistance is negligible. Its combined friction and windage losses are 1.3 kW and its core losses are 0.95 kW. The field current is constant at no-load. Its full load armature current is 55 A at 0.9PF lagging. Assume phase voltage is a reference. Determine following:

a) Its terminal voltage when it is loaded with the rated current at a power factor of 0.9 lagging

b) Its terminal voltage when it is loaded with the rated current at a power factor of 0.9 leading

Hence,

Answer for a (0.9 lagging) should equal VT= 433.59 V

Answer for b (0.9 leading) should equal VT= 512.486 V

Design voltage x4 multiplier(Voltage quadrupler) if rms voltage of AC is 220V and frequency is 60Hz