(i) Compare

(a) Mask Programmable Logic Devices, (b) Field Programmable Logic Devices and (c) Field Programmable Gate Arrays.

(ii) Draw an appropriate schematic diagram to describe following programmable logic devices and discuss their advantages and disadvantages.

(a) Programmable Logic Array

(b) Programmable Array Logic

New electric grid elements and technologies are changing the traditional grid model of “generation ? transmission ? distribution ? load.” Identify what these new disruptive technologies and initiatives are and describe the impacts that each of these is likely to have on the traditional grid.

Draw the block diagram of an adapter (also called “Regulated Power Supply”) and explain the function of each block. Explain briefly with proper sketches, how the diodes form the integral part of the adapter design.

Why we need high gain Receiver RF Amplifier? Justify with an example.

(a) Design an FSM (only state diagram and state table) for a 3-bit counter that counts through odd numbers downwards. Assume the reset state to be the lowest value of the counter. Use an active low reset to reset the counter.

(b) Write a behavioral VHDL code that implements the FSM.

(c) Write a VHDL test bench to test the FSM.

Edit question Write a program that merges two files as follows. The two files are in the docsharing which you can download it. One file will contain usernames(usernames.txt):foster001smith023nyuyen002...The other file will contain passwords(passwords.txt):x34rdf3ep43e4rddw32eds22...The program should create a third file matching username and passwords(usernamesPasswords.txt):foster001x34rdf3esmith023p43e4rddnyuyen002w32eds22......Give the user of your programs the option of displaying you output file. CAN ANYONE SOLVE THIS IN C

write a verilog code to implement a digital system that has an odd counter that counts from 1 to 11. Also, this system has an output Y that detects a specific number in the odd counter. Test your code when you detect the number 3, the output Y is 1, if the counter value is set to 3, otherwise 0.

Explain the operation of 12-pulse full controlled rectifier by sketching circuit schema and related waveforms and by giving the fundamental equations. What are the advantages of that circuit?

VHDL Code will not run simulation. What is the problem with my code??

--VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DataMemory16Bits is
Port ( Address_DM : in STD_LOGIC_VECTOR(15 downto 0);
Data_In_DM : in STD_LOGIC_VECTOR(15 downto 0);
Clock : in STD_LOGIC;
We_DM : in STD_LOGIC;
Re_DM : in STD_LOGIC;
Data_Out_DM : out STD_LOGIC_VECTOR(15 downto 0));
end DataMemory16Bits;

architecture Behavioral of DataMemory16Bits is
Type DataMemory16Bits is array(0 to 31) of STD_LOGIC_VECTOR(15 downto 0);
signal memory: DataMemory16Bits;

begin
process (Address_DM, Clock, We_DM, Re_DM)
begin
Data_Out_DM <= (Others=>'Z');
if (Clock='1')
then
if We_DM='1' and Re_DM='0'
then
Memory(to_integer(unsigned(Address_DM))<= Data_In_DM;
end if;
if Re_DM='1' and We_DM='0'
then
Memory(to_integer(unsigned(Data_In_DM)<= Address_DM;
end if;
if Re_DM='1' and We_DM='1'
then
Data_Out_DM<=Memory(to_integer(unsigned(Address_DM);
else
Data_Out_DM<=(Others=>'Z');
end if;
end if;
end process;
end Behavioral;

We want to make a machine that detects an alternating pattern. It should indicate whether

three or more alternating bits have been observed on our serial input X. So, if X has 010 or

101, the output Z will be high, otherwise the output will be low. Assume that when the

machine starts up or is reset, is has not seen any bits of data to work with and the output

cannot go high until it sees the third bit of data.

Your task is to design two CONCEPTUALLY different synchronous state machines (Mealy

and Moore) in Logisim. You can use either J-K or D flip-flops.

Your Task:

Make the State Diagram

Make the State Assignments

Make the State Transition Table

Make the K-Maps

Derive the Equations

Implement in Logisim

Write a Behavioral model VHDL code that implements an ALU that can perform addition, subtraction, multiplication, shift right, shift left, logical NAND, and logical NOR. Write a VHDL test bench to test the ALU with at least one test vector per operation.

A company plans to purchase a transformer that will be used 12 hours at full load and 12 hours with no load but still connected to the power supply at all times. The transformer has copper losses of 5 kW and core losses of 3.5 kW. Electricity costs $0.07/kW-hr. What is the total cost of transformer losses over a period of 1 year?

A company plans to purchase a transformer that will be used 12 hours at full load and 12 hours with no load but still connected to the power supply at all times. The transformer has copper losses of 5 kW and core losses of 3.5 kW. Electricity costs $0.07/kW-hr. What is the total cost of transformer losses over a period of 1 year?

why differentrial signalling is better then common?