3- (10 pts) Make a status table for a 3-bit
counter that with input x = 1...
3- (10 pts) Make a status table for a 3-bit
counter that with input x = 1 counts the odd numbers and with input
x = 0 counts the even numbers backwards.
You are to design an 4 bit counter that takes as input a clock
and a reset signal and outputs a 4-bit count When the clock is
asserted and the reset is high, the clock increments. When it
increments at 1111,it resets to 0000
Create a schematic diagram of your design using either Xilinx
ISE or a drawing tool of your choice or a neatly hand-drawn
diagram
Create a Verilog module within Xilinx.
Verify your design is syntactically correct.
Create...
(a) Design an FSM (only state diagram and state table) for a
3-bit counter that counts through odd numbers downwards. Assume the
reset state to be the lowest value of the counter. Use an active
low reset to reset the counter.
(b) Write a behavioral VHDL code that implements the FSM.
(c) Write a VHDL test bench to test the FSM.
21a. Draw the state graph and corresponding transition table for
a 3-bit counter with no control inputs that counts in multiples of
3. That is, the count sequence is: 000-011-110-000-.... Use don't
cares in the transition table as appropriate.
b. Draw the state graph and corresponding transition table for a
3-bit binary counter with no control inputs which counts down
rather than up. Include a Z output which signifies when the "count
value modulo 3 is equal to 0."
c....
A binary counter has one input X and counts as follows. If X =
0, it counts 2, 3, 1 and repeats; if X = 1, it counts 1, 0, 3 and
repeats. You can assume that the following cases do not occur:
counter value is 0 with X = 0, and counter value is 2 with X =
1.
(a) Draw the state diagram of the binary counter above. Use the
binary counting values as the state names. You...
Problem 5. (10 pts) In a differential amplifier, the
non-inverting input is 3 cos (600t
+ 45◦) mV and the inverting input is 4cos (600t - 45◦) mV. The
output is vo = 3cos (600t + 45◦) + 4.004cos (600t - 45◦) V. The
CMRR is dB
(a) Design a 4-bit ring counter. Use an external asynchronous
INIT input to initialize the flip-flops to a valid initial state.
Also remember to hook up the CLOCK to all flip-flops.
(b) Design a 4-bit Johnson counter. Use an external asynchronous
INIT input to initialize the flip-flops to a valid initial state.
Also remember to hook up the CLOCK to all flip-flops.
(c) How many states does the ring counter in part (a) have? How
many states does the Johnson...
(10 pts) Draw the result of hashing 11, 22, 3, and 43 into a
table using the following hash function, using separate
chaining:
h(x) = x % 4
0
1
2
3
(10 pts) Draw the result of hashing 11, 22, 3, and 43 into a
table using the following hash function, using open
addressing with linear probing:
h(x) = x % 4
0
1
2
3
Assume a 10-bit data sequence, D = 1100101001 and generator
polynomial, P(X) = X^4 + X^3 + X + 1.
a. Calculate FCS and indicate the transmitted bit sequence.
b. In the class, we learned that a bit error in the data portion
can be detected at the receiver. Can the receiver detect a bit
error if it happens in the FCS field? Show an example by assuming
that the last two bits in the FCS field are in error.
1. (a) ( 10 pts) In ABC City, the length X of residence of a
family in a home is normal with mean 80 months and variance 900.
Using the table, find the probability that a family selected at
random will have lived in ABC City at least eight years.
(b) (5 pts) Using part (a) find the probability that of twelve
independent families living in ABC City exactly three will have
lived there at least eight years.