Question

1. You are to design an 4 bit counter that takes as input a clock and a reset signal and outputs a 4-bit count When the clock is asserted and the reset is high, the clock increments. When it increments at 1111,it resets to 0000
2. Create a schematic diagram of your design using either Xilinx ISE or a drawing tool of your choice or a neatly hand-drawn diagram
3. Create a Verilog module within Xilinx.
4. Verify your design is syntactically correct.
5. Create a Test Bench your circuit by creating a Verilog Test Fixture.
6. Run your circuit in simulation using at least three sets of inputs.

Answer 1

the diagram for ripple counter is shown below:

the behavioral Verilog module is shown below:

// Code your design here
module counter(out_count,clk,reset);
input clk,reset;
output reg [3:0] out_count=0;
always@(posedge clk)
begin
if(!reset)
begin
out_count<=0;
end
else
begin
out_count<=out_count+1;
end
end
endmodule

testbench:

// Code your testbench here
// or browse Examples
// Code your testbench here
// or browse Examples
module test();
reg clk,reset;
wire [3:0] out_count;
counter c1(out_count,clk,reset);
initial
begin
clk=0;reset=0;
#2 reset=0;
#4 reset=1;
#40
#4 reset=0;
#4 reset=1;
$finish;
end
initial
forever
#2 clk=~clk;
initial
$monitor("out_count=%b",out_count);
endmodule

output: