Question

1. What is meant by logical effort. Discuss the logical effort of a 3 input, NAND and NOR gates

Answer 1

Definitions of logical effort:

Logical effort captures enough information about a logic gate’s topology—the network of transistors that connect the gate’s output to the power supply and to ground—to determine the delay of the logic gate.

Definition 1 :The logical effort of a logic gate is defined as the number of times worse it is at delivering output current than would be an inverter with identical input capacitance.

Definition 2 :The logical effort of a logic gate is defined as the ratio of its input capacitance to that of an inverter that delivers equal output current.

Definition 3: The logical effort of a logic gate is defined as the slope of the gate’s delay vs. fanout curve divided by the slope of an inverter’s delay vs. fanout curve.

The logical effort of an input group is defined analogously to the logical effort per input, shown in the previous section. The analog of Definition2 is: the logical effort gbof an input group b is just

NAND gate:
A NAND gate with n inputs, designed to have the same output drive as the reference inverter, will have a series connection of pulldown transistors, each of width n, and a parallel connection of pullup transistors, each of width . Using Equation 1, the total logical effort is:

The logical effort per input is just 1=n of this value, because the input capacitance is equally distributed among the ninputs. below table includes the expressions for logical effort and calculations for several common cases: = 2, n = 2; 3; 4. Note from the equation that the logical effort changes only slightly for a wide range of : when ranges from 1 to 3, the total logical effort for n = 2ranges from 3 to 2.5

NOR gate
The n-input NOR gate consists of a parallel connection of pulldown transistors, each of width 1, and a series connection of pullup transistors, each of width n .The total logical effort is therefore:

Again, the logical effort per input is just 1=ntimes this value. below Table includes examples of the logical effort of a NOR gate. For CMOS processes in which > 1, the logical effort of a NOR gate is greater than that of a NAND gate. If the CMOS fabrication process were perfectly symmetric, so that we could choose = 1, then the logical effort of NAND and NOR gates would be equal.

Table:Summary of calculations of the logical effort of logic gates