Question

find rise time and fall time and logical effort for 5 input NAND gate

sketch 5 input NAND gate, then add the capacitors in order to find the rise time and the falling time ( delays)

Answer 1

consider I_n1 , I_n2 , I_n3 , I_n4 , I_n5   to be the inputs of 5-input NAND gate.

The figure below shows the capacitors in order to find rise and fall time

in above fig if I_n1 = I_n3 = I_n4 = I_n5 =1 . I_n2 =0. I_n2 switches from low to high. hence n-mos transistors except with input I_n1 remaining all are already discharges to ground. In order for V_out to go from high to low V_out node and node 2 must be discharged.

C_load = C_gd6 + C_gd7 + 2C_gd8 + C_gd9 + C_gd10 + C_db6+ C_db7 + C_db8 + C_db9 + C_db10 + C_gd1 + C_gs1 + C_db1 +C_sb1 + 2C_gd2 + 2C_db2 + C_w

note: the vale of C _load for calculating propagation delay depends on which capacitance's need to discharged or charged when the critical signal arrives.

to find rise time

1. worst case rise time is given by : t_r = 0.69 * R_p *C_L

2. best case rise time is given by : t_r = 0.69 * R_p /2 *C_L

to find fall time : t_f = 0.69 * R_n *C_L

logical effort:

logical effort of the entire gate is the ratio of its output logic effort to the sum of its input logic efforts.

the logical effort of the output of gate is sum of the widths of all transistors whose source or drain is in contact with the output node. the logical effort of each input to the gate is sum of the widths of all transistors whose gate is in contact with that input node.

for 5-input NAND gate the logical effort is

in general the logical effort for NAND gate is given by ; where n is the number of inputs.