Question

1. Using Moore machine approach design a sequence detector with one input and one output. When input sequence 010 occurs the output becomes 1 and remains 1 until the sequence 010 occurs again in which case the
output returns to 0. The output remains 0 until, 010 occurs the third time, and so on. Your design should be able to handle overlapping sequences, i.e., input sequence 11001010100 should produce the output 00000110011.
Implement your detector using D flip-flops and the combinatorial gates of your
choice in Behavioral Verilog. Design a behavioral test
circuit which generates the test sequence shown above: ”11001010100”.

Code in VERILOG

Answer 1

module moore_fsm (clk, rst,w, z);
input clk;
input rst;
input w;
output reg z;

parameter S0 = 3'b000,
S1 = 3'b000,
S2 = 3'b010,
S3 = 3'b011,
S4 = 3'b100,
S5 = 3'b101;

//Internal reg and wires decalarations
reg [2:0] cur_state, next_state;

// current state logic
always @(posedge clk)
begin
if(rst)
cur_state <= S0;
else
cur_state <= next_state;
end

// Logic for next state and output
always @(*)
begin
case(cur_state)
S0 : begin
z = 1'b0;
next_state = w ? S0 : S1;
end

S1 : begin
z = 1'b0;
next_state = w ? S2 : S1;
end

S2 : begin
z = 1'b0;
next_state = w ? S0 : S1;
end

S3 : begin
z = 1'b1;
next_state = w ? S4 : S3;
end

S4 : begin
z = 1'b1;
next_state = w ? S5 : S1;
end

S5 : begin
z = 1'b1;
next_state = w ? S5 : S3;
end

default : begin
z = 1'b0;
next_state = S0;
end
endcase
end

endmodule

module moore_fsm_tb;
// Inputs
reg clk;
reg rst;
reg w;

// Outputs
wire z;

// Instantiate the Unit Under Test (UUT)
moore_fsm uut (
   .clk(clk),
   .rst(rst),
   .w(w),
   .z(z)
);

always
#5 clk = !clk;

initial
begin
$monitor("rst = %d, w = %d, z = %d", rst, w, z);
       // Initialize Inputs
       clk = 1'b0; rst = 1'b1;
       w = 1'b1; #10;
       rst = 1'b0;
       w = 1'b1; #10;
       w = 1'b1; #10;
       w = 1'b0; #10;
       w = 1'b0; #10;
       w = 1'b1; #10;
       w = 1'b0; #10;
       w = 1'b1; #10;
       w = 1'b0; #10;
       w = 1'b1; #10;
       w = 1'b0; #10;
       w = 1'b0; #10;
   $finish;
end
  
endmodule