Question

1. Using behavioral VHDL, design a Moore-type finite state machine that detects input test vector that contains the sequence of ‘100’. If the sequence ‘100’ is detected, the output Z should go high. The input is to be named W, the output is to be named Z, a Clock input is to be used and an active low reset signal (Resetn) should asynchronously reset the machine.

a) Draw the Moore-type model state diagram for the FSM.

b) Write the VHDL code to implement the FSM.

Answer 1

a)

(b)

--VHDL Code

library ieee;
use ieee.std_logic_1164.all;

entity moore_sm is
   port (   clock   : in std_logic;
       Resetn   : in std_logic;
       W   : in std_logic;
       Z   : out std_logic
   );
end moore_sm;

architecture arch of moore_sm is

type state is (S0, S1, S2, S3);

signal current_state, next_state : state;

begin

   process (clock, Resetn)
   begin
       if (Resetn = '0') then
           current_state <= S0;
       else
           if rising_edge (clock) then
               current_state <= next_state;
           end if;
       end if;
   end process;

   process(current_state, W)
   begin

       case (current_state) is
           when S0=>   if (W = '1') then
                       next_state <= S1;
                   else
                       next_state <= S0;
                   end if;
                   Z   <= '0';

           when S1=>   if (W = '0') then
                       next_state <= S2;
                   else
                       next_state <= S1;
                   end if;
                   Z   <= '0';

           when S2=>   if (W = '1') then
                       next_state <= S1;
                   else
                       next_state <= S3;
                   end if;
                   Z   <= '0';

           when S3=>   if (W = '1') then
                       next_state <= S1;
                   else
                       next_state <= S0;
                   end if;
                   Z   <= '1';

           when others=>    null;

       end case;

   end process;

end arch;

----------------------------------------------------------------------------------------------------------------------------------------------------------------------

--Testbench

library IEEE;
use IEEE.Std_logic_1164.all;

entity moore_sm_tb is
end;

architecture bench of moore_sm_tb is

component moore_sm
   port (   clock   : in std_logic;
       Resetn   : in std_logic;
       W   : in std_logic;
       Z   : out std_logic
   );
end component;

signal clock: std_logic;
signal Resetn: std_logic;
signal W: std_logic;
signal Z: std_logic ;
  
begin

uut: moore_sm port map ( clock => clock,
Resetn => Resetn,
W => W,
Z => Z );

stimulus: process
begin
   Resetn    <= '0';
   W   <= '1';

   wait for 10 ns;

   W   <= '0';
   wait for 40 ns;

   W   <= '1';
   wait for 60 ns;

   Resetn    <= '1';
   W   <= '1';
   wait for 60 ns;

   W   <= '0';
   wait for 20 ns;

   W   <= '0';
   wait for 20 ns;

   W   <= '0';
   wait for 20 ns;
   wait;
  
end process;

clocking: process
begin
   clock <= '0';
   wait for 10 ns;
clock <= '1';
   wait for 10 ns;
end process;

end;

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--Simulated on ModelSim