Design a system with one input called “Up” such that when “Up” equals 1, the machine...

Design a system with one input called “Up” such that when “Up” equals 1, the machine counts 2, 3, 4, 5, 6, and repeat. If the “Up” input equals 0, the machine counts down 6, 5, 4, 3, 2, and repeat.

Show the State Transition Diagram, State Transition table, K-maps, and equations assuming JK flip flops and AND/OR/NOT combinational logic. Make sure to indicate on your State Transition Diagram what happens if the system initially is in one of the unused states (0, 1, or 7).

Expert Solution

Input	Present State			Next State			JK Flip Flop Inputs
Up	Q2	Q1	Q0	Q2+	Q1+	Q0+	J2	K2	J1	K1	J0	K0
0	0	0	0	1	1	0	1	X	1	X	0	X
0	0	0	1	1	1	0	1	X	1	X	X	1
0	0	1	0	1	1	0	1	X	X	0	0	X
0	0	1	1	0	1	0	0	X	X	0	X	1
0	1	0	0	0	1	1	X	1	1	X	1	X
0	1	0	1	1	0	0	X	0	0	X	X	1
0	1	1	0	1	0	1	X	0	X	1	1	X
0	1	1	1	1	1	0	X	0	X	0	X	1
1	0	0	0	0	1	0	0	X	1	X	0	X
1	0	0	1	0	1	0	0	X	1	X	X	1
1	0	1	0	0	1	1	0	X	X	0	1	X
1	0	1	1	1	0	0	1	X	X	1	X	1
1	1	0	0	1	0	1	X	0	0	X	1	X
1	1	0	1	1	1	0	X	0	1	X	X	1
1	1	1	0	0	1	0	X	1	X	0	0	X
1	1	1	1	0	1	0	X	1	X	0	X	1

When Down Counting, i.e. Up = 0, then unused states 0,1,7 transits to state 6

When UP Counting, i.e. Up = 1, then unused states 0,1,7 transits to state 2

Excitation Table of JK Flip Flop

Q	Q+	J	K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

LogiSim is used to design the circuit as per K-Map deduced equations for JK Flops.

Manojponduru answered 2 years ago

1. Using Moore machine approach design a sequence detector with one input and one output. When...

1. Using Moore machine approach design a sequence detector with one input and one output. When input sequence 010 occurs the output becomes 1 and remains 1 until the sequence 010 occurs again in which case the output returns to 0. The output remains 0 until, 010 occurs the third time, and so on. Your design should be able to handle overlapping sequences, i.e., input sequence 11001010100 should produce the output 00000110011. Implement your detector using D flip-flops and the...

Consider a finite state machine with a control input called mode. When mode = 0, the...

Consider a finite state machine with a control input called mode. When mode = 0, the machine operates as a mod-3 down counter, where the outputs are the count values. When mode = 1, the machine's output progresses through the last 4 digits of your WCU ID (1133) number (1 digit per clock cycle). Complete each of the steps which follow. (a) Draw the state diagram for this machine. (b) Write RTL Verilog code which implements this design. Submit your...

What is a solution called when the concentration of the solute equals its solubility in the solvent?

What is a solution called when the concentration of the solute equals its solubility in the solvent? a) Dilute b) Saturated c) Unsaturated d) Supersaturated

Design a Moore state machine that has an input w and an output z that should...

Design a Moore state machine that has an input w and an output z that should output a ‘1’ when the previous 4 values of w were 1001 or 1111. Overlapping patterns are allowed. Show the state diagram and state table. Use a simple binary counting order for the state assignment. Derive all of the next-state and output equations. You do not need to draw the resulting circuit, instead write a Verilog module for it.

1.) A.) In a 5V system if you were asked to take one input HIGH and...

1.) A.) In a 5V system if you were asked to take one input HIGH and another LOW what would you do (i.e. where would you connect them)? B.) If Vcc is 5.0V in CMOS logic, what are the acceptable high and low levels for the inputs? C.) If Vcc is 5.0V in CMOS logic, what are the acceptable high and low levels for the outputs? D.) You can directly connect any of the ICs from one logic family to...

Design B: Using behavioral VHDL, design a Mealy-type finite state machine that detects input test vector...

Design B: Using behavioral VHDL, design a Mealy-type finite state machine that detects input test vector that contains the sequence of ‘10’. If the sequence ‘10’ is detected, the output Z should go high. The input is to be named W, the output is to be named Z, a Clock input is to be used and an active low reset signal (Resetn) should asynchronously reset the machine. a) Draw the Mealy-type state diagram for the FSM. b) Write the VHDL...

Design a mealy machine that generates the output Z=1 when it detects an even number of...

Design a mealy machine that generates the output Z=1 when it detects an even number of 1s and odd number of zeros. Draw the state table and circuit diagram for it with D flipflops. Example of input is 00101 Example of output is 10011

A) Design 0?379 count?up counter with BCD counter blocks if input clear signal is synchronous. B) Design...

A) Design 0?379 count?up counter with BCD counter blocks if input clear signal is synchronous. B) Design 0?379 count?up counter with BCD counter blocks if input clear signal is Asynchronous. C) Design of 1/577 frequency divider with BCD count?up counters (Clear signal is Asynchronous)

Design JavaFX application with 7 labels and one textfield where user enters input inches. When user enters...

Design JavaFX application with 7 labels and one textfield where user enters input inches. When user enters his choice and presses enter key to complete input, program outputs resulting yards, feet, and inches. Use class P5 that extends Application with start method in it, and class P5Pane that extend GridPane. The only inctance variables for P5Pane class are inputInches where user enters input inches, and three labels: outYards, outFeet, and outInches where program displays result of conversion. Use the following names for instance variables:...

1. What is one benefit of system upgrades? A. All of the above B. Receiving input...

1. What is one benefit of system upgrades? A. All of the above B. Receiving input on the product C. Improved response quality D. Meaningful interaction with the end user 2. Which of the following is not a step of the Software Development Life Cycle? A. Demonstration B. Maintenance C. Installation D. Analysis 3. Which symbol is placed on any association that occurs between an actor and a procedure? A. [E] B. [C] C. Both [E] and [C] D. [I]...

Question