Make a schema for a memory size of 65536 words per 8 bits. Use 8k by 8-bit...

Make a schema for a memory size of 65536 words per 8 bits. Use 8k by 8-bit 2764 memory a) with a single decoder 388 and inverters. b) Use a decoder 2 4 and inverters? Help? How to implement?

Expert Solution

Schematic for 64Kx8 memory using 8Kx8 chips and 3x8 decoder

Schematic diagram of 64Kx8 memory using 8Kx8 chips , two 2x4 decoders and one inverter

I used the same principle in both designs a , b

I.e basically address decoding using available decoders in both cases using ( A15-A13) address lines as input to decoder and using the decoder outputs to drive chip select of respective memory chip (8Kx8)

As u know in decoder once only one outout will be high so at a particular input address only one memory chip will be active to load or store data in specified memory location

Manojponduru answered 1 year ago

The followings are 8-bit words is stored in the memory. Suppose when the words were read...

The followings are 8-bit words is stored in the memory. Suppose when the words were read from the memory, the check bits are calculated to be 0010. Using Hamming error correction code, find the he check bits stored together with the word, the syndrome word and the word fetched from the memory for the word given below. 0110 1010 1111 0001

A 64 bit computer uses a memory of 32KB. Work out the number of bits of...

A 64 bit computer uses a memory of 32KB. Work out the number of bits of AR, DR, PC, AC, and the HEX code of the address of last memory location. b) The memory attached to a processor has access time of 400ns. When a cache memory is introduced in the system, it is found that on average the access time for the computer was 30% greater than the cache access time for a miss ratio of 0.10. Work out...

IEEE 754 format of 32-bit floating-point is as follows. 1 8 (bits) 23 (bits) What’s stored...

IEEE 754 format of 32-bit floating-point is as follows. 1 8 (bits) 23 (bits) What’s stored in each region? What’s the bias value and how to get it? For decimal fraction: – 0.625, please represent it as given format (Note: you must show the specific procedure/stepsin order to get full credits. If you only present final result directly, you will only get half of the credits even if it is correct.).

13. A digital computer has a memory unit with 32 bits per word. The instruction set...

13. A digital computer has a memory unit with 32 bits per word. The instruction set consists of 260 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are left for the address part of the instruction? c) What is the maximum allowable size for memory? d) What...

A digital computer has a memory unit with 32 bits per word. The instruction set consists...

A digital computer has a memory unit with 32 bits per word. The instruction set consists of 122 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are left for the address part of the instruction? c) What is the maximum allowable size for memory? d) What is...

Interpret these signed 8-bit sequences with each type of signed/unsigned encoding. Remember the bits are arbitrary!...

Interpret these signed 8-bit sequences with each type of signed/unsigned encoding. Remember the bits are arbitrary! They can be interpreted in many different ways. C.1: Complete the following table using decimal (base-10) numbers. The first line is already completed for you bit sequence unsigned sign-magnitude 1s’ complement 2’s complement 00000101 +5 +5 +5 +5 11110001 ? ? ? ? 01010011 ? ? ? ? 10000000 ? ? ? ? 11111111 ? ? ? ?

A direct mapped cache has 16 blocks and block size is 64-bits (8 bytes). a. Where...

A direct mapped cache has 16 blocks and block size is 64-bits (8 bytes). a. Where will the memory block 45 reside in cache? (5 b. Where will be the memory address 1667 mapped in cache

Design and Test an 8-bit Adder using 4-bit adder. Use 4-bit adder coded in class using...

Design and Test an 8-bit Adder using 4-bit adder. Use 4-bit adder coded in class using full adder that is coded using data flow model. Use test bench to test 8-bit adder and consider at least five different test vectors to test it.

Using the following VHDL code for an 8 bit adder, make the sum be displayed on...

Using the following VHDL code for an 8 bit adder, make the sum be displayed on the seven segment display of an Elbert V2 Spartan 3A FPGA Board. VHDL: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity state_bit_adder is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; D : in STD_LOGIC; Enable : out STD_LOGIC_vector (2 downto 0); input: in std_logic_vector(7 downto 0); SUM: out...

6. Assume a computer has a physical memory organized into 64-bit words. Using hexadecimal notation, give...

6. Assume a computer has a physical memory organized into 64-bit words. Using hexadecimal notation, give the word address and offset within the word for each of the following byte addresses. Byte address Word address Offset 0x000b 0x03ff 0x07fc

Question