Question

In: Computer Science

A direct mapped cache has 16 blocks and block size is 64-bits (8 bytes). a. Where...

A direct mapped cache has 16 blocks and block size is 64-bits (8 bytes).

a. Where will the memory block 45 reside in cache? (5

b. Where will be the memory address 1667 mapped in cache

Solutions

Expert Solution

SOLUTION

In a directed mapped cache , consecutive memory locations are stored in form of blocks inside the cache in a defined order. A cache with N blocks will try to store N memory blocks inside it (for faster memory accesses later on) and this storage of blocks is done systematically and consecutively. Whenever a memory block that needs to be accessed and is not currently in the cache , it is accessed from the main memory and this step is called a cache miss. On the contrary , if one of the blocks contains the address that needs to be accessed , then the address is accessed much wuickly from the cache and this step is called a cache hit.

PROBLEM A :

Cache can only store = 16 blocks.

Each block has memory = 64 bits = 8 bytes.

Assuming the memory to be byte addressable , the cache has = 16*8 bytes = 128 bytes of memory.

Now , blocks are placed consecutively inside a cache. Block number (1,2,......,15,16) is stored in the cache and if we need to access some other block, then all 16 blocks are replaced.

For eg: we want to access Block number 22 , then Cache will be replaced with (17,18,....31,32).

So , we can see that Block number B will be at a position B%16.

Therefore , block number 45 would be at = 45 MOD 16 = 13th position in the cache.

PROBLEM B :

Assuming the memory to be byte adressable ,

1667th memory adddress is present in = 1667/8 = 208.375th block.

Now , 208th block is present at 208 MOD 16 = 0th block ( which is nothing but the 16th block , as X MOD Y becomes 0 when X is a multiple of Y)

Hence , 1667th memory address is present in 16th block.


Related Solutions

A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes...
A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine the block is missing and bring it into cache.) Assume a request is always started in parallel to both cache and to main memory(so if it is not found in cache, we do not have to...
Assume a computer with a cache that holds 64 bytes and has a block size of...
Assume a computer with a cache that holds 64 bytes and has a block size of 32 bytes. Direct address mapping is used and from the beginning the cache is empty. The following program sequence is executed: for (col = 0; col < 2; col++) { for (row = 0; row < 4; row++) A[row][col] = B[row] * C[col]; } Assume that for the variables row and col registers are used. The matrix A consists of 4 rows and 4...
Below are listed parameters for different direct-mapped cache designs. Cache Data Size: 32 KiB Cache Block...
Below are listed parameters for different direct-mapped cache designs. Cache Data Size: 32 KiB Cache Block Size: 2 words Cache Access Time: 1 cycle Word: 4 bytes. Calculate the total number of bits required for the cache listed above, assuming a 32-bit address. Given that total size, find the total size of the closest direct-mapped cache with 16-word blocks of equal size or greater. Explain why the second cache, despite its larger data size, might provide slower performance than the...
For a direct mapped cache design with 32 bit address, the following bits of the address...
For a direct mapped cache design with 32 bit address, the following bits of the address are used to access the cache Tag Index Offset 31 - 8 7 - 4 3 - 0 What is the cache block size (in words)? How many entries does the cache have? What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded. Address 0...
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a...
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. For fully associative cache, to which block of cache the address 0x189B5A maps? Group of answer choices Block 6 Block 75 Not enough information Block 10
Suppose we have a direct-mapped cache that can hold a total of 1024 blocks with 4...
Suppose we have a direct-mapped cache that can hold a total of 1024 blocks with 4 words per block. Compute the block index, block offset, and the tag for the following addresses: (a) 0x11001001 (b) 0x00010014 (c) 0x01000004 (d) 0x01001018 (e) 0x7bdcca10
a) consider a direct mapped cache with 10 blocks of 10 words each. Suppose main memory...
a) consider a direct mapped cache with 10 blocks of 10 words each. Suppose main memory is 1000 words. For ewach memory address below say what cache block it maps to, what is the offset, and what is the tag. 934, 666, 348, 522
A direct mapped cache has 32 cache lines.Each cache line consists of 4 words, and each...
A direct mapped cache has 32 cache lines.Each cache line consists of 4 words, and each word is four bytes.The address bus consists of 16 bits. How many bits are required for the tag in this direct-mapped cache?
Given an 8-word, direct mapped cache, and the sequence of address accesses below, enter the number...
Given an 8-word, direct mapped cache, and the sequence of address accesses below, enter the number of misses. CACHE CONFIG 24 13 24 10 8 8 Given an 8-word, 2-way set associative cache, and the sequence of address accesses below, enter the number of misses. CACHE CONFIG 22 1 9 22 22 22 Given an 8-word, 2-way set associative cache, and the sequence of address accesses below, enter the number of misses. CACHE CONFIG 23 23 8 20 9 20...
Ethernet (10Mbps) frames must be at least 64 bytes (512 bits) long to ensure that the...
Ethernet (10Mbps) frames must be at least 64 bytes (512 bits) long to ensure that the transmitter is still going in the event of a collision at the far end of the cable. Fast Ethernet (100Mbps) has the same 64-byte minimum frame size but can get the bits out ten times faster. How is it possible to maintain the same minimum frame size?
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT