Question

In: Computer Science

13. A digital computer has a memory unit with 32 bits per word. The instruction set...

13. A digital computer has a memory unit with 32 bits per word. The instruction set consists of 260 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory.

a) How many bits are needed for the opcode?

b) How many bits are left for the address part of the instruction?

c) What is the maximum allowable size for memory?

d) What is the largest unsigned binary number that can be accommodated in one word of memory?

Solutions

Expert Solution

Greetings!!

ANSWER ( a ) :

The instruction set consists of 260 different operations.
So you should make room for each one instruction, meaning 260 unique instruction.
Therefore, bits that are needed for the opcode :-
=>Ceiling[ Log2(260) ]
=> 9 bits

ANSWER ( b ) :

Now, the remaining bits that are left for the address part of the instruction :-
   => No. of bits per word - No. of bits needed for the opcode
   => 32 - 9
   => 23 bits

ANSWER ( c ) :
Since we have 32 bits per word and we have 23 bits for address part.
Therefore, the maximum allowable size for memory is:-
   => 223 * 32 bits

ANSWER ( d ) :

Here we have 32 bits per word, so the largest unsigned binary number that can be accommodated in one word of memory:
   => 232 – 1

***********************************************************************************************************************************

**If you have any doubts then ask in comments. If you like the solution then please give it a thumbs up :)


Related Solutions

In a computer instruction format, the instruction length is 11 bits and the size of an...
In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4 bits. Is it possible to have 5 two-address instructions 45 one-address instructions 32 zero-address instructions using the specified format? Justify your answer.
In a computer instruction format, the instruction length is 12 bits and the size of an...
In a computer instruction format, the instruction length is 12 bits and the size of an address field is 5 bits. The system architect has already designed three 2-address instructions and thirty one 1-address instructions. How many 0-address instructions can still be possibly accommodated?
A digital signal has four levels. How many bits are needed per level? Draw the digital...
A digital signal has four levels. How many bits are needed per level? Draw the digital signal assume the baud rate is 8 baud per second. Increasing the levels of a signal increases the probability of an error occurring, in other words it reduces the reliability of the system. Why and how can this be resolve? What determines how successful a receiver will be in interpreting an incoming signal? Spectrum of a channel between 5 MHz and 4 MHz; SNRdB...
Computer Architecture 1. Define what a "word" is in computer architecture: The size (number of bits)...
Computer Architecture 1. Define what a "word" is in computer architecture: The size (number of bits) of the address The total number of bits of an instruction (e.g. 16 bits) Word and width are synonymous. A word is the contents of a memory register. 2. What is the difference between a register’s width and a register’s address? (choose all that apply - there may be more than one correct answer) They are both the same! Address is the same for...
A 64 bit computer uses a memory of 32KB. Work out the number of bits of...
A 64 bit computer uses a memory of 32KB. Work out the number of bits of AR, DR, PC, AC, and the HEX code of the address of last memory location. b) The memory attached to a processor has access time of 400ns. When a cache memory is introduced in the system, it is found that on average the access time for the computer was 30% greater than the cache access time for a miss ratio of 0.10. Work out...
Example: A 3-address computer has 40 instructions, 16 Registers, and 256KB memory. Assume each instruction has...
Example: A 3-address computer has 40 instructions, 16 Registers, and 256KB memory. Assume each instruction has three operands. Two registers and the third operand is a direct address location of a memory. Find minimum size of PC, MAR, MDR, IR. Solution: OPCODE R1, R2, address OPCODE is 6 bits since 2^6>40 Register field is 4 bits since 2^4 =16 Memory field is 18 bits since 2^18=256K Instruction length =6+4+4+18=32 bits MDR=32 bits IR=32 bits MAR=18 PC=18 Please explain
Design a random-access digital memory that can write or read single bits in two addressable SRFFs...
Design a random-access digital memory that can write or read single bits in two addressable SRFFs having 3-bit addresses 5 and 7. The memory has the following inputs and outputs. Address input lines A2, A1, A0, Data input line DIN, and Data output line DOUT, Read/Write input line RW (RW = 0 stores DIN into addressed memory. RW = 1 puts addressed memory data on DOUT)
Make a schema for a memory size of 65536 words per 8 bits. Use 8k  by 8-bit...
Make a schema for a memory size of 65536 words per 8 bits. Use 8k  by 8-bit 2764 memory a) with a single decoder 388 and inverters. b) Use a decoder 2 4 and inverters? Help?   How to implement?
Xion Co. budgets a selling price of $91 per unit, variable costs of $32 per unit,...
Xion Co. budgets a selling price of $91 per unit, variable costs of $32 per unit, and total fixed costs of $290,000. During June, the company produced and sold 12,800 units and incurred actual variable costs of $371,000 and actual fixed costs of $305,000. Actual sales for June were $1,190,000. Prepare a flexible budget report showing variances between budgeted and actual results. List variable and fixed expenses separately. (Indicate the effect of each variance by selecting for favorable, unfavorable, and...
The following 32-bit binary word written in hexadecimal format represents a single RISC-V assembly instruction. What...
The following 32-bit binary word written in hexadecimal format represents a single RISC-V assembly instruction. What is the RISC-V instruction format and specific assembly language instruction? 0xfe810113
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT