Question

Using behavioral VHDL, design a Mealy-type finite state machine that detects input test vector that contains the sequence of ‘100’. If the sequence ‘100’ is detected, the output Z should go high. The input is to be named W, the output is to be named Z, a Clock input is to be used and an active low reset signal (Resetn) should asynchronously reset the machine. a) Draw the Mealy-type state diagram for the FSM. b) Write the VHDL code to implement the FSM.

Answer 1

- VHDL code for above required MEALY state diagram

--standard logic library declaration
library IEEE;
use IEEE.std_logic_1164.all;

--entity declaration for Mealy machine
entity VHDL_MEALY_FSM is
port (
clock: in std_logic; --- clock signal
resetn: in std_logic; -- reset input
W: in std_logic; -- binary sequence input
Z: out std_logic -- output of the VHDL sequence detector
);
end VHDL_MEALY_FSM;

--architecture behavioral model of Mealy state machine
architecture Behavioral of VHDL_MEALY_FSM is

--state definitions
type state is (A,B,C);

--internal signal declartions for states
signal current_state, next_state: state;

begin
-- Sequential present state logic of the VHDL Mealy FSM
process(clock,resetn)
begin
if(resetn='0') then
current_state <= A; -- upon reset initial state assumed as A
elsif(rising_edge(clock)) then
current_state <= next_state;
end if;
end process;

-- Next state logic of the VHDL Mealy FSM
-- Combinational logic
process(current_state,W)
begin
case(current_state) is
when A =>
if(W ='1') then
next_state <= B; Z <= '0';
else
next_state <= A; Z <= '0';
end if;
when B =>
if(W ='1') then
next_state <= B; Z <= '0';
else
next_state <= C; Z <= '0';
end if;
when C =>
if(W ='1') then
next_state <= B; Z <= '0';
else
next_state <= A; Z <= '1';
end if;

  
end case;
end process;



end Behavioral;

-- testbench

-- Code your testbench
library IEEE;
use IEEE.std_logic_1164.all;

--entity declaration for testbench
entity test_FSM is
end test_FSM;

--architecture body declaration for testbench
architecture behavioral of test_FSM is

--component declaartion for FSM
component VHDL_MEALY_FSM is
Port (
clock: in std_logic; --- clock signal
resetn: in std_logic; -- reset input
W: in std_logic; -- binary sequence input
Z: out std_logic -- output of the VHDL sequence detector
);
end component;

--internal signal declarations
signal clock: std_logic;
signal resetn: std_logic;
signal W: std_logic;
signal Z: std_logic;

begin
--instantiate DUT fsm
DUT: VHDL_MEALY_FSM port map ( clock => clock ,
resetn => resetn ,
W => W,
Z => Z );

--clock process
clk_process:process
begin
clock <= '1';
wait for 5 ns;
clock <= '0';
wait for 5 ns;
end process;


--input stimuus process
stim_proc:process
begin
W <= '0'; resetn <= '1';
wait for 10 ns;
W <= '1'; resetn <= '0';
wait for 10 ns;
W <= '0'; resetn <= '1';
wait for 10 ns;
W <= '0'; resetn <= '0';
wait for 10 ns;
W <= '1'; resetn <= '1';
wait for 10 ns;
W <= '0'; resetn <= '1';
wait for 10 ns;
W <= '0'; resetn <= '1';
wait for 10 ns;
W <= '1'; resetn <= '1';
wait for 10 ns;
W <= '0'; resetn <= '1';
wait for 10 ns;
W <= '1'; resetn <= '1';
wait for 10 ns;
W <= '1'; resetn <= '1';
wait for 10 ns;
W <= '0'; resetn <= '1';
wait for 10 ns;
W <= '0'; resetn <= '1';
wait for 10 ns;
W <= '1'; resetn <= '1';
wait;


end process;

end behavioral;

-- simulated waveforms