In: Electrical Engineering
Consider a finite state machine with a control input called mode. When mode = 0, the machine operates as a mod-3 down counter, where the outputs are the count values. When mode = 1, the machine's output progresses through the last 4 digits of your WCU ID (1133) number (1 digit per clock cycle). Complete each of the steps which follow.
(a) Draw the state diagram for this machine.
(b) Write RTL Verilog code which implements this design. Submit
your printed source code by the due date and time.
(c) Create a test bench to exercise the design through all of its
states and functions. Submit your test bench source code and a
simulation waveform. The simulation waveform must show the digits
of your WCU ID and no one else's.
(b)
module fsm (clock, mode, Q);
input clock, mode;
output reg [1:0] Q;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
reg [2:0] current_state, next_state = 3'b000;
always @ (posedge clock)
begin
current_state <= next_state;
end
always @ (current_state, mode)
begin
case (current_state)
S0: next_state <= S1;
S1: if (mode == 1'b1) next_state
<= S3; else next_state <= S2;
S2: if (mode == 1'b1) next_state
<= S1; else next_state <= S0;
S3: if (mode == 1'b1) next_state
<= S4; else next_state <= S0;
S4: if (mode == 1'b1) next_state
<= S5; else next_state <= S0;
S5: if (mode == 1'b1) next_state
<= S1; else next_state <= S0;
default : next_state <= S0;
endcase
end
always @ (current_state)
begin
case (current_state)
S0: Q <= 2'b00;
S1: Q <= 2'b01;
S2: Q <= 2'b10;
S3: Q <= 2'b01;
S4: Q <= 2'b11;
S5: Q <= 2'b11;
default : Q <= 2'b00;
endcase
end
endmodule
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(c)
module tb_fsm ();
reg clock, mode;
wire [1:0] Q;
fsm uut (clock, mode, Q);
initial begin
clock = 1'b0;
mode = 1'b0;
#100;
mode = 1'b1;
#50;
mode = 1'b0;
end
always #5 clock = ~clock;
endmodule
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