Question

In: Electrical Engineering

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Vendingvhdl IS PORT( Clk : IN &

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY Vendingvhdl IS

PORT(

Clk : IN STD_LOGIC;

Change : OUT STD_LOGIC_VECTOR(1 downto 0);

Inputs : IN STD_LOGIC_VECTOR(1 downto 0);

output : OUT STD_LOGIC);

END Vendingvhdl;

ARCHITECTURE vending of Vendingvhdl IS

TYPE STATE_TYPE IS (empty, fivecent, tencent, ready);

SIGNAL current_state, next_state : STATE_TYPE;

BEGIN

Combinational LOGIC

COMBINE: PROCESS (inputs)

BEGIN

CASE current_state IS

When empty =>

IF inputs = “00” THEN

next_state <= empty;

output <= ‘0’;

change <= “00”;

ELSEIF inputs = “01” THEN

next_state <= fivecent;

output <= ‘0’;

change <= “00”;

ELSEIF inputs = “10” THEN

next_state <= tencent;

output <= ‘0’;

change <= “00”;

ELSEIF inputs = “11” THEN

next_state <= ready;

output <= ‘1’;

change <= “10”;

ENDIF;

WHEN fivecent =>

IF inputs = “00” THEN

next_state <= fivecent;

output <= ‘0’;

change <= “00”;

ELSEIF inputs = “01” THEN

next_state <= tencent;

output <= ‘0’;

change <= “00”;

ELSEIF inputs = “10” THEN

next_state <= ready;

output <= ‘0’;

change <= “00”;

ELSEIF inputs = “11” THEN

next_state <= ready;

output <= ‘1’;

change <= “01”;

change <= “10”;

ENDIF;

WHEN tencent =>

IF inputs = “00” THEN

next_state <= tencent;

output <= ‘0’;

change <= “00”;

ELSEIF inputs = “01” THEN

next_state <= ready;

output <= ‘1’;

change <= “00”;

ELSEIF inputs = “10” THEN

next_state <= ready;

output <= ‘1’;

change <= “00”;

ELSEIF inputs = “11” THEN

next_state <= ready;

output <= ‘1’;

change <= “01”;

change <= “10”;

Please complete the following VHDL code...I am implementing a simple vending machine FSM

Expert Solution

-- Here it is understood from code snipet that cost of good is 15 cent. Hence two more states added to return 10 or 20 ---cents based on inputs

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY Vendingvhdl IS

PORT(

Clk : IN STD_LOGIC;

Change : OUT STD_LOGIC_VECTOR(1 downto 0);

Inputs : IN STD_LOGIC_VECTOR(1 downto 0);

output : OUT STD_LOGIC);

END Vendingvhdl;

ARCHITECTURE vending of Vendingvhdl IS

TYPE STATE_TYPE IS (empty, fivecent, tencent, return15, return20,ready);

SIGNAL current_state, next_state : STATE_TYPE;

BEGIN

process(clk)

begin

if rising_edge (Clk) then

current_state <= next_state;

end if;

end process;

COMBINE: PROCESS (current_state, inputs)

BEGIN

CASE current_state IS

When empty =>

IF inputs = "00" then

next_state <= empty;

output <= '0';

change <= "00";

ELSIF inputs = "01" THEN

next_state <= fivecent;

output <= '0';

change <= "00";

ELSIF inputs = "10" THEN

next_state <= tencent;

output <= '0';

change <= "00";

ELSIF inputs = "11" THEN

next_state <= ready;

output <= '1';

change <= "10";

END IF;

When fivecent =>

IF inputs = "00" then

next_state <= fivecent;

output <= '0';

change <= "00";

ELSIF inputs = "01" THEN

next_state <= tencent;

output <= '0';

change <= "00";

ELSIF inputs = "10" THEN

next_state <= ready;

output <= '1';

change <= "00";

ELSIF inputs = "11" THEN

next_state <= return15;

output <= '1';

change <= "01";

END IF;

When return15 =>

next_state <= ready;

change <= "10";

When tencent =>

IF inputs = "00" then

next_state <= tencent;

output <= '0';

change <= "00";

ELSIF inputs = "01" THEN

next_state <= ready;

output <= '1';

change <= "00";

ELSIF inputs = "10" THEN

next_state <= ready;

output <= '1';

change <= "01";

ELSIF inputs = "11" THEN

next_state <= return20;

output <= '1';

change <= "10";

END IF;

When return20 => next_state <= ready;

change <= "10";

When ready => next_state <= empty;

end case;

end process;

end vending;

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Question

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Vendingvhdl IS PORT( Clk : IN &

Solutions

Expert Solution

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