Question

Derive a minimal state table for a Moore model FSM that acts as a three-bit parity generator. For every three bits that are observed on inputw during three consecutive clock cycles, the FSM generates the parity bit outputq = 1 if the number of 1s received in the sequence so far is odd. Thus, this is an even parity generator. Implement the FSM as a circuit in Logisim Evolution.

Note that the FSM outputs a 1 as long as the number of 1s received so far in the three-bit sequence is odd. This means that the circuit can output 1s before receiving all three bits. An example of this would be receiving the input 1 at the start; the circuit will output 1 after seeing the 1. Had the FSM received a 0 instead, the circuit would output 0. If the circuit receives a 0 after receiving the 1, the circuit would output 1 again. Note that after receiving the three bits, the circuit resets and starts looking at the next three bit set; thus, this is not a sliding window.

Answer 1

Minimal state table for a Moore model FSM that acts as a three-bit parity generator is shown in below image.