Question

In VHDL with Xilinx Vivado, design a PWM circuit as described in the Background and Theory section. The central part will be 0 to 9 counter, with an integrated comparator. VHDL supports < and > as comparisons. You will just need to integrate a PWM output into the counter. For simulation, use a 10 kHz clock to the counter, which will result in a 1 kHz PWM signal. Simulate a 0%, 30%, 70% and 100% duty cycle.

Answer 1

library ieee;

use ieee.std_logic_1164.all;

entity pwm is

port

( clk : in std_logic;

pwm_out : buffer std_logic

);

end entity;

architecture rtl of pwm is

begin

process (clk)

--variable to count the clock pulse

variable count : integer range 0 to 50000;

--variable to change duty cycle of the pulse

variable duty_cycle : integer range 0 to 50000;

--variable to determine whether to increse or decrese the dutycycle

variable flag : integer range 0 to 1;

begin

if (rising_edge(clk)) then

--increasing the count for each clock cycle

count= count+1;

--setting output to logic 1 when count reach duty cycle value

--output stays at logic 1 @ duty_cycle <= count <=50000

if (count = duty_cycle then

pwm_out <= '0';

count:= 0;

--after each complete pulse the duty cycle varies

if(flag = 0) then

duty_cycle:= duty_cycle+50;

else

duty_cycle:= duty_cycle-50;

end if;

-- flag changes when duty_cycle reaches max and min value

if(duty_cycle = 50000) then

flag:= 1;

elseif(duty_cycle = 0) then

flag:= 0;

end if;

end if;

end if;

end process;

end rtl;