I need a synthesizable Verilog code/module implementing the IEEE 754 Floating Point multiplication and a corresponding...

I need a synthesizable Verilog code/module implementing the IEEE 754 Floating Point multiplication and a corresponding test bench. It should set a flag for underflow and overflow conditions if they arise during the multiplication for the output. It would be greatly appreciated if someone could write this floating point multiplication code in Verilog with some comment lines so i could understand the functioning too with a test bench module ! I have tried to explain everything as clearly as possible and really hope someone can help me out here !

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Manojponduru answered 1 year ago

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