Question

Consider a secure communication channel where communication will start if the receiver detects the following sequence:

A=1, B=0 --> A=0, B=0 --> A=0, B=1

Draw a FSM state diagram with 2 inputs, first input (A), and second input (B), 1 output signal: correct sequence (Seq_detected). Create a Verilog code for this FSM and use the testbench to verify its correct operation.

Even just a state diagram would help. Thanks

Answer 1

We implement Moore State Machine for the intended sequence detector.

Its corresponding state diagram is shown below-

Here on the archs we represent inputs in format AB

//Verilog Code

module receiver (clock, A, B, Z);

input clock, A, B;
output reg Z;
parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
reg [1:0] current_state, next_state;

always @ (posedge clock)
   current_state <= next_state;

always @ (current_state or A or B)
begin
   case (current_state)
       2'b00 : begin
           Z <= 1'b0;
           if (A == 1'b1 && B == 1'b0)
               next_state <= S1;
           else
               next_state <= S0; end

       2'b01 : begin
           Z <= 1'b0;
           if (A == 1'b0 && B == 1'b0)
               next_state <= S2;
           else
               next_state <= S0; end

       2'b10 : begin
           Z <= 1'b0;
           if (A == 1'b0 && B == 1'b1)
               next_state <= S3;
           else
               next_state <= S0; end

       2'b11 : begin
           Z <= 1'b1;
           if (A == 1'b1 && B == 1'b0)
               next_state <= S1;
           else
               next_state <= S0; end

       default : next_state <= S0;
   endcase
end

endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//Testbench

module tb_receiver;

reg clock, A, B;
wire Z;

receiver uut (clock, A, B, Z);

initial begin

   clock    <= 1'b0;
   A   <= 1'b0;
   B   <= 1'b0;

   #30;
   A   <= 1'b1;
   B   <= 1'b0;
  
   #10;
   A   <= 1'b0;
   B   <= 1'b0;

   #10;
   A   <= 1'b0;
   B   <= 1'b1;

   #20;
   A   <= 1'b1;
   B   <= 1'b1;
  
   #10;
   A   <= 1'b0;
   B   <= 1'b1;

   #10;
   A   <= 1'b1;
   B   <= 1'b0;  

end

always #5 clock = ~clock;

endmodule

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//Simulated on ModelSim