Question 1A:Convert the following FSM into Circuit There are 6 states, 5 inputs and 1 output....

Question 1A:Convert the following FSM into Circuit There are 6 states, 5 inputs and 1 output.

1B: Write the Verilog Code using the FSM in Question 1A Question

1C: Write the Verilog Code using the Circuit (controller) in Question 1A.

1D: Write a test bench to test the code in Question 1B as well as in 1C. The same test bench will be used for Verilog Behavioral code (question 1B) and Verilog Structural code (Question 1C).

1E: Generate the timing diagram using simulator (preferable). If the simulator is not available, then draw the diagrams manually.

Expert Solution

PLEASE UPVOTE IT'S NEEDED PLEASE : )

venereology answered 2 years ago

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