Design a digital circuit for output ‘e’ for the seven segment
display for all possible inputs.
Inputs: ABCD
a
f b
g
e c
d
A) Derive a truth table
B) Design using K-Map technique, a minimum AND-OR gate network
for this system. Draw the resulting digital circuit diagram
2. A sequential circuit has two pulse inputs, x1 and x2. The
output of the circuit becomes 1 whenever the pulse sequence
x1x1x2x2x2x1 is detected. The output then remains 1 for all
subsequent x1 pulses until an x2 pulse occurs.
(a) Derive a minimal state table describing the circuit
operation. (Here you need to define the states and then perform
state reduction).
(b) Synthesize the circuit using SR latches in the master rank.
(Here, you need to make state assignment,...
Question 1A:Convert the following FSM into Circuit There are 6
states, 5 inputs and 1 output.
1B: Write the Verilog Code using the FSM in Question 1A
Question
1C: Write the Verilog Code using the Circuit (controller) in
Question 1A.
1D: Write a test bench to test the code in Question 1B as well
as in 1C. The same test bench will be used for Verilog Behavioral
code (question 1B) and Verilog Structural code (Question 1C).
1E: Generate the timing...
Consider a sequential circuit to
control the washer:
The circuit receives 3 input signals: Clock, DoorOpen, and
Start. It also maintains a state bit Wash.
If DoorOpen = 1, Wash should be set to 0.
Otherwise, if Start = 1, Wash should be set to 1 and if Start =
0, Wash should retain its value from previous cycle.
Make A truth table to compute the new value of Wash;
Make A circuit Diagram.
------------------------------------
How would the truth table...
Design a sequential circuit with 2 JK flip-flops A and B, and 2 inputs, E and x. the design must adhere to the following requirements: If E = 0, the circuit remains in the same state regardless of the value of x. When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00 and repeats. When E = 1 and x = 0, the circuit goes through the...
design a logic circuit that counts the number of 1s in 12
inputs(a0...a11) and outputs a 4-bit binary that represents the
count of 1s. for example, if input is 111111111111 which has 12 1s,
then output should be 1100
note :Do not use clocking. draw logic diagram.
Suppose that you design an amplifier circuit but measuring the
output on the oscilloscope shows that it is just oscillating
wildly. List the first three things to check to understand what is
causing the oscillation.
design an electro- pneumatic circuit with three
cylinder output .the process will be in sequence the cylinder 1
extend , cylinder 2 then cylinder 3(using Timers). draw the
pneumatic circuit including directional control valve and cylinders
etc.. draw the electric circuit of pneumatic circuit including
switches, relays , timer etc..
if possible include the conveyor motor in
electric circuit.
Design a clocked synchronous state machine with two inputs, A and B, and a single output Z that is 1 if
(1) A had the “different” value at each of the two previous clock ticks, or
(2) B has been 1 since the last time that the first condition was true.
Otherwise, the output should be 0.
Design state assignment using decomposed method. D Use flip-flops to a minimum, and design the next-state logic with a minimal 2-level NAND-NAND circuit....