Question

Do the type-D and JK flip flops respond to the same clock edge?

Explain how toggle mode is the same as division by two.

What is the difference between a synchronous input (D, J, or K) and an asynchronous input (PR or CLR)?

*please no handwritten answers

Answer 1

1) Yes,D-type flip-flop can just like the JK flip-flop be converted to perform as a toggle flip-flop by connecting the Q output directly to the D-input with the toggling signal T being the clock input . Connecting the Q to the input creates negative feedback.

2) A Toggle flip-flop got its name from the fact that it has ability to toggle between two different states:

• The toggle state
• The memory state.
• Since there are only two states, a T-type flip-flop is ideal for use in frequency division and binary counter design.
• Each time we add another T-type flip-flop to the chain, the output clock frequency is halved or divided-by-2 again and so on, giving an output frequency of 2n where “n” is the number of flip-flops used in the sequence.
• Hence toggle mode freq is same as divide by 2.

3) synchronous input

• memory elements are clocked flip-flops, for instance D-type flip-flops, which change state when a transition of the clock signal occurs.
• Due to the techniques used to design the flip-flops, the sensitivity of these elements to their inputs exists only in a short time interval.
• 

asynchronous input

• There is no "explicit" memory element to store the current state.
• the state is stored in feedback loops that exist in the circuit, which is made exclusively with basic combinational gates.
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