In: Electrical Engineering
Deserializer
Explain how this circuit works. Note that these flip-flops are positive edge-triggered.
What requirements of setup time, hold time, and propagation delay must be met for this circuit to work?
Imagine that clock had a slow rising edge (for example, it could be coming through a long path from a separate circuit board, or the clock driver might be undersized). Considering that, due to random mismatch, each flip-flop will trigger at a slightly different threshold, what behavior could result from a clock edge that's too slow? What circuit(s) could be used to ameleorate potential misbehavior?