Question

In: Other

A sequential circuit has two JK flip-flops A and B, two inputs r and y,...



A sequential circuit has two JK flip-flops A and B, two inputs r and y, and one output z. The flip-flop input equations and circuit output equation are 

\(\begin{aligned} J_{A} &=A^{\prime} x+B^{\prime} y & K_{A}=B x^{\prime} y^{\prime} \\ J_{B} &=A^{\prime} x y & K_{B}=A^{\prime}+B^{\prime} x \\ z &=A^{\prime} x^{\prime}+B^{\prime} y^{\prime} & \end{aligned}\)

(a) Derive the simplified state equations for A and B. 

(b) Tabulate the state table. 

(c) Draw the state diagram of the çircuit.


S.10 A sequential circuit has two JK flip-flops A and B, two inputs r and y, and one outpu. The flip-flop input equations and circuit output equation are KB A+ B (a) Derive the simplified state equations for A and B. (b) Tabulate the state table. (c) Draw the state diagram of the çircuit.

Solutions

Expert Solution

(a) Simplified state equations for A and B.

first consider the characteristic equation of any flip-flop:

where Q(t+1) is the next state and Q(t) is current state.

so,

where left hand side A is the next A and right hand side A is current A.

again for B

(b) state table:

A       B x y A    B    J(A) K(A) J(B) K(B) Z      
0 0 0 0 0 0 0 0 0 1 1
0 0 0 1 1 0 1 0 0 1 1
0 0 1 0 1 0 1 0 0 1 1
0 0 1 1 1 1 1 0 1 1 0
0 1 0 0 0 0 0 1 0 1 1
0 1 0 1 0 0 0 0 0 1 1
0 1 1 0 1 0 1 0 0 1 0
0 1 1 1 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 0 0 1
1 0 0 1 1 0 1 0 0 0 0
1 0 1 0 1 0 1 0 0 1 1
1 0 1 1 1 0 1 0 0 1 0
1 1 0 0 0 1 0 1 0 0 0
1 1 0 1 1 1 0 0 0 0 0
1 1 1 0 1 1 1 0 0 0 0
1 1 1 1 1 1 1 0 0 0 0

(c)

state diagram:


Related Solutions

Design a sequential circuit with 2 JK flip-flops A and B, and 2 inputs, E...
Design a sequential circuit with 2 JK flip-flops A and B, and 2 inputs, E and x. the design must adhere to the following requirements: If E = 0, the circuit remains in the same state regardless of the value of x.  When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00 and repeats. When E = 1 and x = 0, the circuit goes through the...
Attach a screenshot of Multisim circuit. flip flops: D, T and JK, connect the circuit and...
Attach a screenshot of Multisim circuit. flip flops: D, T and JK, connect the circuit and verify the characteristic tables.
Use JK-Flip-Flop to design a sequential circuit as an input for the previous designed decoder to...
Use JK-Flip-Flop to design a sequential circuit as an input for the previous designed decoder to write UAE. In this design, the sequential circuit will be used instead of the two bits switches and the output will be shown in three 7-segment displays one for each letter. Letters must glow one by one in a correct sequence where the speed depends on the clock frequency. Use only one circuit as an input for the three 7-segment displays where one of...
Design a 5-bit binary counter using JK flip flops. Draw the flip-flop circuit diagram, the state...
Design a 5-bit binary counter using JK flip flops. Draw the flip-flop circuit diagram, the state graph, the timing diagram, the truth table (with clk pulse) and the state table (with present and next states).
Design sequential circuit for detect 11011 sequence using D flip flops clearly indicating the procedure and...
Design sequential circuit for detect 11011 sequence using D flip flops clearly indicating the procedure and relevant diagrams. Write vrilog code for your circuit. Step by step answers please.
2. A sequential circuit has two pulse inputs, x1 and x2. The output of the circuit...
2. A sequential circuit has two pulse inputs, x1 and x2. The output of the circuit becomes 1 whenever the pulse sequence x1x1x2x2x2x1 is detected. The output then remains 1 for all subsequent x1 pulses until an x2 pulse occurs. (a) Derive a minimal state table describing the circuit operation. (Here you need to define the states and then perform state reduction). (b) Synthesize the circuit using SR latches in the master rank. (Here, you need to make state assignment,...
I want to make 5 sec counter from 1000Hz input frequency using D or JK flip-flops....
I want to make 5 sec counter from 1000Hz input frequency using D or JK flip-flops. Anyone can help me with logic circuits and excitation table. Also, 5-bit parallel load register with flipflop.
1. (20pts) Design a 3-bit counter that counts from 0000 to 1111 using JK flip/flops. Do...
1. (20pts) Design a 3-bit counter that counts from 0000 to 1111 using JK flip/flops. Do not forget to include the carry to detect overflow.
Design an up/down counter with four states (0, 1, 2, 3) using clocked JK flip flops....
Design an up/down counter with four states (0, 1, 2, 3) using clocked JK flip flops. A control signal x is used as follows: When x = 0 the machine counts forward (up), when x = 1, backward (down). Simulate using MultiSim and attach a simulation printout. Please address the following: State Table State Diagram Flip Flop Excitation Tables K-Map Simplification and Resulting Diagram MultiSim Simulation
Deserializer Explain how this circuit works. Note that these flip-flops are positive edge-triggered. What requirements of...
Deserializer Explain how this circuit works. Note that these flip-flops are positive edge-triggered. What requirements of setup time, hold time, and propagation delay must be met for this circuit to work? Imagine that clock had a slow rising edge (for example, it could be coming through a long path from a separate circuit board, or the clock driver might be undersized). Considering that, due to random mismatch, each flip-flop will trigger at a slightly different threshold, what behavior could result...
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT