I want to make 5 sec counter from 1000Hz input frequency using D
or JK flip-flops. Anyone can help me with logic circuits and
excitation table. Also, 5-bit parallel load register with
flipflop.
Design a Count-up Counter in Aiken code with following flip
flops: a) D-FF (Active edge is high to low) b) SR-FF (Active edge
is high to low) c) Use of output of circuit in part (b) and minimum
number of logic gates for getting the Countdown counter in Aiken
code
Design a 5-bit binary counter using JK flip flops.
Draw the flip-flop circuit diagram, the state graph, the timing
diagram, the truth table (with clk pulse) and the state table (with
present and next states).
Design a synchronous counter, using T flip-flops, that has the
following sequence: 0010, 0110, 1000, 1001, 1100, 1101, and repeat.
From the undesired states the counter must always go to 0010 on the
next clock pulse.
Design an up/down counter with four states (0, 1, 2, 3) using
clocked JK flip flops. A control signal x is used as follows: When
x = 0 the machine counts forward (up), when x = 1, backward (down).
Simulate using MultiSim and attach a simulation printout.
Please address the following:
State Table
State Diagram
Flip Flop Excitation Tables
K-Map Simplification and Resulting Diagram
MultiSim Simulation