Question

In Verilog

Design a state machine, using the D flip-flop, that implements a 00 and 11 sequence detector. Your machine should output a 1 as soon as it detects two 0s or two 1s on its input, otherwise it outputs 0s.
Write a module that implements the machine and a test bench to test it.

Answer 1

Answer 1)

Verilog code in behavioral style is mentioned below. the code is written with the help of the state diagram.

module moore_00_11 (clk, rst, x, z);
input clk;
input rst;
input x;
output reg z;

parameter S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;

//Internal reg and wires decalarations
reg [2:0] cur_state, next_state;

// current state logic
always @(posedge clk)
begin
if(rst)
cur_state <= S0;
else
cur_state <= next_state;
end

// Logic for next state and output
always @(*)
begin
case(cur_state)
S0 : begin
z = 1'b0;
next_state = x ? S1 : S2;
end

S1 : begin
z = 1'b0;
next_state = x ? S3 : S0;
end

S2 : begin
z = 1'b1;
next_state = x ? S1 : S2;
end

S3 : begin
z = 1'b1;
next_state = x ? S3 : S0;
end
default : begin
z = 1'b0;
next_state = S0;
end
endcase
end

endmodule

Testbench for the verilog code

module testbench;
reg clk;
reg rst;
reg x;
wire z;

moore_00_11 u_fsm_moore (.clk(clk), .rst(rst), .x(x), .z(z));

always
#5 clk = !clk;

initial
begin
   clk = 1'b0;
   rst = 1'b1;
x = 1'b0;
repeat(2)
   @(negedge clk);
   rst = 1'b0;
x = 1'b1;
   @(negedge clk);
   x = 1'b0;
   @(negedge clk);
   x = 1'b1;
   @(negedge clk);
x = 1'b0;
repeat(3)
   @(negedge clk);
x = 1'b1;
   @(negedge clk);
x = 1'b0;
   @(negedge clk);
x = 1'b1;
   @(negedge clk);
x = 1'b0;
   @(negedge clk);
x = 1'b1;
repeat(5)
   @(negedge clk);

   $finish;
end

initial
begin
$recordfile("file1.trn");
$recordvars();
end

endmodule

Waveform:-