Question

Design a synchronous counter of four-bit using D flip‐flops and gates (AND, OR etc.)

*use verilog language modules and test and explain briefly

Answer 1

the following contains Verilog code:

truth table:

Verilog code:

module d_ff(d,q,qbar,clk);// the main element d_ff
  input d,clk;
  output reg q=1;
  output qbar;
  assign qbar=~q;
  always@(posedge clk)
    begin
      q=d;
      //qbar=~q;
    end
endmodule

module d_ff(d,q,qbar,clk);
input d,clk;
output reg q;
output qbar;
assign qbar=~q;
always@(posedge clk)
begin
q=d;
end
endmodule

module up_counter(q_out,clk);
input clk;
output reg [3:0] q_out;
wire w1,w2,w3,w4;
d_ff d11(~q_out[0],q_out[0],w1,clk);// instanciating the d_Ff made above in order to make the above diagram
d_ff d22((q_out[1]^q_out[0]),q_out[1],w2,clk);
d_ff d33((q_out[2]&~(q_out[0])+q_out[2]&~(q_out[1])+~(q_out[2])&q_out[1]&q_out[0]),q_out[2],w3,clk);
d_ff d44((q_out[3]&~(q_out[2])+q_out[3]&~(q_out[0])+q_out[3]&(~q_out[1])+~(q_out[3])&q_out[2]&q_out[1]&q_out[0]),q_out[3],w4,clk);
endmodule
  

testbench:

// Code your testbench here
// or browse Examples
module test();
reg clk;
wire [3:0] q_out;
up_counter u1(q_out,clk);
initial
begin
clk=0;
#100 $finish;
end
initial
forever
#2 clk=~clk;// clock generator
initial
$monitor("q_out=%b",q_out);
initial
begin
$dumpfile("dump.vcd");// creating varible dump file for waveform viewing
$dumpvars(1);
end
endmodule