Question

Design a full adder using discrete logic devices in LogicWorks. Make the full adder into a component (or subcircuit) and save in a personal library for future use.Cascade sixteen full adders to create a 16-bit ripple-carry adder. Make the sixteen-bit ripple carry adder into a component and store in your library.Connect hexkeypads from the LogicWorks IOconnect library to the inputs of the adder to test the circuit. Connect hexdisplays from the same library to provide the results for testing.Determine how long it takes the correct answer to stabilize after an input is applied, in gate delays. (Assume AND, OR, and Inverters have one unit of gate delay and XOR’s have two units.)Find input values that will demonstrate the ripple nature of the adder.

Answer 1

Part 1: Adder Implementations

The aim of this part of the exercise  is to get acquainted with different implementations of adders.  You will introduce a ripple- carry adder and a  carry look- ahead adder in this section of the exercise.  You will generate a standard (XOR / AND / OR)  implementation and the associated NAND / NAND implementation for both implementations.  Set the delays of the gates in all sub- circuits according  to the table given in the General Information section above.

Using the standard implementation (using XOR / AND /  OR gates) and NAND / NAND implementation, implement a Full- Adder.  For each one of  these implementations, build a subcircuit.  According to the following  naming convention, name the implementation:

• Full-Adder (standard): FA_S
• Full-Adder (NAND-NAND): FA_N

Implement a 4-bit ripple-carry adder (one with FA S  and one with FA N) using these full adders.  Measure the delay of these  adders for different input combinations.  An adder 's delay is the time difference between the time when  you change the input and the time when the output no longer changes.  In your delay measurements, please include  the addition of (1111 to 0001).  Try the worst case delay (or  critical path delay) to get it.  Describe the worst case delay in  your report.

Implement an adder  with a carry-look- ahead.  In your implementation,  follow these steps.

• To generate 'generate' and 'propagate' words for the  carry-look-ahead adder, create a subcircuit with 2 4-bit inputs. Implement a circuit with a carry-look-ahead generator.  G0 ... g3, p0 ... p3 and  c0.0 should be the inputs to this circuit.  This circuit 's output should be  c1 ... c4 & g(0,3), p(0,3).
• Develop a 4-bit carry-look-ahead  adder, combining the building blocks.  Inputs for this circuit are supposed to be  x0 ... x3, y0 ... y3

Part 2: Logic Functions

The aim of this part of the  exercise is to learn about hazard- free circuit implementation.  You are provided the  exact functions in this portion:

F₁(w,x,y,z) = w'z+wxy'+wy'z'
F₂(w,x,y,z) = w'x+wy+xy+w'y'z
F₃(w,x,y,z) = (x+z)(w+x')(x'+y'+z')
F₄(w,x,y,z) = (w'+y)(w+x'+z')(x'+y+z')(w'+x'+z)

The  Requirements:  

For the first part, along with the results that you are asked to send  in in the first part of this hand- out (delays, etc.), send in all your designs.  Indicate which functions have static hazards for the second  half, describe these hazards and describe when they happen.  Also, transform in a circuit that implements the same feature  in a hazard- free way for each circuit containing a hazard.