A 3 phase 450V (line-to-line), 1150rpm induction machine has the following equivalent circuit parameters. R1=0.33 Ohms, X1=1.3Ohms R2 = 0.25 Ohms X2 = 40Ohms. Determine the following: a) Rated stator current (per-phase) b) Input power factor c) Total power across the air gap d) The full-load torque e) Magnitude of the starting current

If up to 40% of an engineer's working time spent writing and communicating, why is communication not a more substantial and significant part of an engineering students educational training?

Design and implement a sequential circuit that counts from 0-3 in a repeating cycle with two inputs: step and reset. If the step input is 1 the count progresses to the next value, if 0 you stay at the current value. If the reset input is 1 the count returns to 0, if 0 it has no effect. If both step and reset are 1, reset takes precedence.
Use J-K flip flops in your design and follow the design process outlined:
• Derive a state diagram for the circuit
• Create a state table
• Derive the flip-flop input equations and output equations
• Draw the logic diagram
• Implement the logic circuit on your breadboard for presentation

comparison of class A and class B amplifiers ?

Explain about three-phase resonant converters ?

1. Given    V=100V    R=10kΩ    C=10µF    (10 pts)

1. Determine the mathematical expression for v_c

2. Determine the mathematical expression for i_c

3. Computer the capacitor voltage at t=150 ms

4. Computer the capacitor current at t=150 ms

5. Locate the points on the voltage and current curves.

Plot the effect of proportional (Kp), integral (Ki), and derivative (Kd) gains to a step-change in an error signal, e(t). At least make three plots (1-3), each containing three graphs:

1. Graph 1 High Kp; graph2: medium Kp; graph 3: low Kp

2. Graph 1: Low Kd; Graph 2: medium Kd; Graph 3: high Kd

3. Graph 1: High Kp and Ki; Graph 2: medium Kp, Ki, and Kd; Graph 3: low Kp and Ki

If you're not answering all three parts of this question, don't answer it.

Consider the following FSM VHDL code:

library ieee;

use ieee.numeric_std.all;

entity fsm is

port (clock, input, reset: in std_logic;

output: out std_logic_vector (2 downto 0));

end;

architecture bhv of fsm is

type state is (s1, s2, s3, s4);

signal sreg: state;

begin

sreg_machine: process (clock)

begin

if (reset='1') then

sreg <= s1;

output <= "000";

elsif (rising_edge(clk)) then

case sreg is

when s1=>

output <= "000";

if (input='0') then

sreg <= s2;

else

sreg <= s1;

end if;

when s2=>

output <= "010";

if (input='1') then

sreg <= s4;

else

sreg <= s3;

end if;

when s3=>

output <= "100";

if (input='0') then

sreg <= s1;

else

sreg <= s4;

end if;

when s4=>

output <= "101";

if (input='0') then

sreg <= s4;

else

sreg <= s3;

end if;

end case;

end if;

end process;

end architecture;

a) Draw the state diagram for this FSM.

b) What kind of FSM is this? Mealy or Moore? Why?

c) Do you see issues with this FSM VHDL code for simulation or synthesis? List your answers (if any) and explain how you fix the coding issue.

(a) Explain the principle of transformer action.
(b) Derive an expression for the e.m.f. induced in a transformer winding. Show that emf per turn in primary is equal to e.m.f. per turn in the secondary.

Six poles, 60 [Hz], and three super-executive induction motors have total load revolutions of 1,050 [rpm]. In order to rotate it to 1000 rpm on the same torque, determine what external resistance [ohm] should be inserted into the secondary side. However, the second side has r2 resistance in the Y duel.

A factory need a drive system for a conveyer system. Voltage source available is three phase 415
Volt, 50 Hz. Electric motor that they use is DC motor.
(i) How the design of DC drive system for that system :
(ii) What the parameters should be considered?
(iii) What type of the DC motor that needed?
(iv) What kind of converters that suitable for this system?
(v) How the control system?

Write VHDL code (behavior model) to implement a 4-bit modulo-9 counter and simulate your VHDL code of 4-bit modulo-9 counter in ModelSim, and capture the screenshot

of your simulated waveform.

Assume clock period Tclk=100ns, initially, the counter is reset to Q₃Q₂Q₁Q₀=0000 you need to simulate a complete counting cycle plus one more additional clock period after it is reset to “0000” state.

Design a 4-to-1 multiplexer using VHDL

a- use with-select-when statement in writing VHDL file

generate timing diagram

QUIESTION 1
A three-phase synchronous generator is connected to an infinite bus. The infinite bus voltage and the generated voltage are o 1.0 pu ∠0 and o 1.0pu ∠42.84 , respectively. The synchronous reactance is 0.85 pu and resistances are neglected. a) Compute power angle (δ), armature current (Is), power factor (pf), real power (P), and reactive power (Q). Draw the phasor diagram. b) If the prime mover torque is kept constant at a value corresponding to P=0.8 pu, compute the required value of the generated voltage (E2) for the unity power factor condition (and constant power, P=0.8 pu). What is the new value of power angle (δ2)? Solution: δ= 42.84o , Is = 0.86pu ∠21.44o , pf=0.93, P=0.8 ph, Q= -0.314pu, δ2 = 34.2o , E2= 1.21pu

QUESTION 2
Two “three-phase Y-connected synchronous generators” have per phase generated voltages of o 1 E = 120 V∠10 and o 2 E = 120 V∠20 under no load, and resistance of X j5 Ω / phase 1 = and X j8 Ω / phase 2 = . They are connected in parallel to a load impedance of XL = 4 + j3 Ω / phase . Compute: a) Per phase terminal voltage Vt (both magnitude and phase angle). b) Armature currents for each generator ( a1 a2 I and I ). c) Power supplied by each generator (P1 and P2 ). d) The total output power (Pout ). Solution: Vt= 82 V ∠-5.94o , Ia1 = 9.36 A ∠-51.17o , Ia2 = 7.31 A ∠-32.06o , P1 = 1621 W, P2 = 1614.5 W, Pout = 3236 W.