In: Electrical Engineering
If you're not answering all three parts of this question, don't answer it.
Consider the following FSM VHDL code:
library ieee;
use ieee.numeric_std.all;
entity fsm is
port (clock, input, reset: in std_logic;
output: out std_logic_vector (2 downto 0));
end;
architecture bhv of fsm is
type state is (s1, s2, s3, s4);
signal sreg: state;
begin
sreg_machine: process (clock)
begin
if (reset='1') then
sreg <= s1;
output <= "000";
elsif (rising_edge(clk)) then
case sreg is
when s1=>
output <= "000";
if (input='0') then
sreg <= s2;
else
sreg <= s1;
end if;
when s2=>
output <= "010";
if (input='1') then
sreg <= s4;
else
sreg <= s3;
end if;
when s3=>
output <= "100";
if (input='0') then
sreg <= s1;
else
sreg <= s4;
end if;
when s4=>
output <= "101";
if (input='0') then
sreg <= s4;
else
sreg <= s3;
end if;
end case;
end if;
end process;
end architecture;
a) Draw the state diagram for this FSM.
b) What kind of FSM is this? Mealy or Moore? Why?
c) Do you see issues with this FSM VHDL code for simulation or synthesis? List your answers (if any) and explain how you fix the coding issue.
a)
b)
Its a Moore State Machine as output depends only on state S1, S2, S3 and S4.
whereas in Mealy output depends on state as well as input.
c)
There are issues like:
(i) Its a single process FSM. Hence state reg updation , output and next state updation is carried out in one process body. As process body execution is sequential, we can observe a single clock delay in output update.
(ii) Synthesis will fail as case statements are not written for all possible sreg conditions as std_logic is 9 valued logic. we include "others" option.
(iii) end of architecture is to be fixed. syntax in "end <architecture name>" or "end"
We have included two process and other changes mentioned above.
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library ieee;
use ieee.numeric_std.all;
entity fsm is
port (clock, input, reset: in std_logic;
output: out std_logic_vector (2 downto 0));
end;
architecture bhv of fsm is
type state is (s1, s2, s3, s4);
signal P_sreg, N_sreg: state;
begin
sreg_machine: process (clock)
begin
if (reset='1') then
P_sreg <= s1;
elsif (rising_edge(clk)) then
P_sreg <= N_sreg;
end if;
end process;
process (P_sreg, input)
begin
case P_sreg is
when s1=>
output <= "000";
if (input='0') then
N_sreg <= s2;
else
N_sreg <= s1;
end if;
when s2=>
output <= "010";
if (input='1') then
N_sreg <= s4;
else
N_sreg <= s3;
end if;
when s3=>
output <= "100";
if (input='0') then
N_sreg <= s1;
else
N_sreg <= s4;
end if;
when s4=>
output <= "101";
if (input='0') then
Nsreg <= s4;
else
N_sreg <= s3;
end if;
when others=> null;
end case;
end process;
end bhv;