Conciderer the full-width rectangular pulses p(t). the rms value of AWGN is 10^-3V.

A) Determine the necessary (minimmum) signal power such that the detection error probability is less the than 10^-5 when polar signaling is used.

B) repeat the problem for on-off signaling.

C) repeat the problem for bipolar signaling.

D) make your comments.

NOTE: Q (4.26)= 10^-5 , Q(4.36)= 0.67x10-5

Give a list of 5 techniques used to produce HVDC

Describe each technique in detail

Design in VHDL a gray code decoder to excess 3 code

Screenshot the simulation and code.

1) Write a program in C++

sin(x) can be approximately calculated using the following formula, where n! is factorial(n) – for example 3!=3*2*1 = 6 (the function in previous problem).

The more terms we use in the series, the higher will be accuracy of the calculations. By using infinite terms in the series we will have the exact value.

Hint 1: For n! simply use (copy and paste) the factorialFunc(n)from previous problem.

Hint 2: This problems is similar to the “pi series” problem in the homework problems. A simple for loop is needed. Much easier that it looks.

Write a program that gets x and calculates sin(x) using 10, 100, 1000 and 10,000 terms.

Then run the program and calculate and display the result for x=pi/6.

Describe three principle components involved in the Western EIM.

What communication advances have led Cybersecurity to be a greater concern to modern SCADA/ICS systems? Explain your answer.

Describe the principle components of the ISO Grid Management System (So called the ISO Grid Control Center).

From information found in the 2N3904’s datasheet (found with Google or on Blackboard), estimate the collector-emitter saturation voltage of the 2N3904 transistor at a collector current of 15 mA. You may perform a linear interpolation between the values found in the datasheet (ie: use the point-gradient formula learned in high school).

Design a Matlab program that records your voice for 5 seconds and then cuts off the low frequencies. Then, have the program play the edited recording.   

Directions: Let’s look at how pipelined execute can be affected by resource hazards, control hazards and instruction set architecture. Looking at the following fragment of code:
ADD X5, X2, x1
LDUR X3, [X5, #4]
LDUR X2, [X2, #0]
ORR X3, X5, X3
STUR X3 [X5, #0]

Assume that all of the branches are perfectly predicted as this eliminates all potential control hazards and that no delay slots will be needed. If we only have one memory for both the instructions and data, there is a structural hazard every time that we need to fetch an instruction in the same cycle which another instruction accesses data. To guarantee that we have forward progress, this structural hazard has to be resolved by giving the favor to the instruction that accesses data.

What would be the total execution time of the sequence in the 5-stage pipeline that only has one memory? Explain your answer.

Assume now that all the branches are perfectly predicted as this eliminates all potential control hazards and that no delay slots will be needed. If we change the load/store instructions to use a register without an offset as the addresses, the instructions would no longer need to use the ALU. As a result, the MEM and EX stages can be overlapped and the pipeline would only now have 4 stages.

Change the code to accommodate the changed ISA. What is the speedup achieved in this instruction sequence? Explain your answer.

Show a pipeline execution diagram for these series of instructions (both initial and end) result.

Please answer the questions accordingly there are three of them.

Please make copy paste available

Describe the basic operation of a transistor