Question

Design a bus arbiter;

A.) Plot the algorithm state chart.

B.)Draw the state table

C.) implement suitable hardware

Answer 1

Assumptions

It is desired that more than one independent processor in system further requirement is that they require access to same set of system resources for external memory size is 64 KB and require a single RD/WR signal. Design a system that accept data from each independent processor and arbitrate which one is granted access to memory at any one time. Each independent processor will initiate a memory-required signal when it wants access to memory and will deactivate the same when the job is over. if more than one processor request for the bus at the same time , access should be granted on round robin basis.

SEQUENCE OF EVENTS: 1) All the three processor have request access to bus either for reading or writing of data from/or to the memory. 2) Since priority of IPA is highest, the arbiter will grant access of buses to A and will deny access of buses to processor B and C as well. 3) The processor A in turn will specify the type of memory reference is memory read or memory write. Using this information arbiter will issue address as provided by processor and respective control signal for memory and the operation is continued. 4) Being in this state, arbiter also keep track of the duration of access (Timeout period) and take appropriate action.

Combinational Output

==> (imp )This is prioritized logic with IP ‘A’ having higest priority & ‘C’ having lowest priority. Thus simultaneous request would lead to access of bus to the IP with higher priority at any instant of time.

Complete hardware structure based on state machine